[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Add configs for enabling DCI and TraceHub

[Aamir Bohra (aamirbohra@gmail.com)]

Aamir Bohra (aamirbohra at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18791

-gerrit

commit 8a837dca3514dae42feed427363d6c2c92c1708e
Author: Aamir Bohra <aamir.bohra at intel.com>
Date:   Mon Feb 6 21:48:48 2017 +0530

    soc/intel/skylake: Add configs for enabling DCI and TraceHub
    
    Add configs for enabling Intel Trace Hub and DCI for aid in debugging.
    
    Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e
    Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
 src/soc/intel/skylake/chip.h                    |  5 +++++
 src/soc/intel/skylake/romstage/romstage_fsp20.c | 22 ++++++++++++++--------
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 69b5364..cd34940 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -157,6 +157,11 @@ struct soc_intel_skylake_config {
 
 	/* Trace Hub function */
 	u8 EnableTraceHub;
+	u32 TraceHubMemReg0Size;
+	u32 TraceHubMemReg1Size;
+
+	/* DCI Enable/Disable */
+	u8 PchDciEn;
 
 	/* Pcie Root Ports */
 	u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index a4bb684..70a9697 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -108,16 +108,12 @@ static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
 	m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
 }
 
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+			const struct soc_intel_skylake_config *config)
 {
-	const struct device *dev;
-	const struct soc_intel_skylake_config *config;
 	int i;
 	uint32_t mask = 0;
 
-	/* Set the parameters for MemoryInit */
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
-	config = dev->chip_info;
 	/*
 	 * Set IGD stolen size to 64MB.  The FBC hardware for skylake does not
 	 * have access to the bios_reserved range so it always assumes 8MB is
@@ -130,7 +126,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
 	m_cfg->ProbelessTrace = config->ProbelessTrace;
-	m_cfg->EnableTraceHub = config->EnableTraceHub;
 	if (vboot_recovery_mode_enabled())
 		m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */
 	else
@@ -151,10 +146,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
+	const struct device *dev;
+	const struct soc_intel_skylake_config *config;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
 
-	soc_memory_init_params(m_cfg);
+	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	config = dev->chip_info;
+
+	soc_memory_init_params(m_cfg, config);
 
 	/* Enable DMI Virtual Channel for ME */
 	m_t_cfg->DmiVcm = 0x01;
@@ -163,6 +163,12 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	m_t_cfg->SendDidMsg = 0x01;
 	m_t_cfg->DidInitStat = 0x01;
 
+	/* DCI and TraceHub configs */
+	m_t_cfg->PchDciEn = config->PchDciEn;
+	m_cfg->EnableTraceHub = config->EnableTraceHub;
+	m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
+	m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
+
 	mainboard_memory_init_params(mupd);
 }