[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Clean up Systemagent code

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18567

-gerrit

commit 079ccd5bcce7979705dd0569bbf954485d47915c
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Tue Mar 14 18:26:27 2017 +0530

    soc/intel/apollolake: Clean up Systemagent code
    
    Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/apollolake/bootblock/bootblock.c     |  2 +-
 src/soc/intel/apollolake/chip.c                    |  2 +-
 src/soc/intel/apollolake/include/soc/northbridge.h | 40 ----------------------
 src/soc/intel/apollolake/include/soc/systemagent.h | 34 ++++++++++++++++++
 src/soc/intel/apollolake/memmap.c                  |  2 +-
 src/soc/intel/apollolake/northbridge.c             |  2 +-
 src/soc/intel/apollolake/romstage.c                |  2 +-
 7 files changed, 39 insertions(+), 45 deletions(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cdf3acf..b1b652a 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -25,7 +25,7 @@
 #include <soc/gpio.h>
 #include <soc/iosf.h>
 #include <soc/mmap_boot.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/uart.h>
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 2973abf..74e9ae9 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -37,7 +37,7 @@
 #include <spi-generic.h>
 #include <soc/pm.h>
 #include <soc/p2sb.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 
 #include "chip.h"
 
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
deleted file mode 100644
index 04e369e..0000000
--- a/src/soc/intel/apollolake/include/soc/northbridge.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
-#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
-
-#define MCHBAR		0x48
-#define PCIEXBAR	0x60
-#define PCIEX_SIZE	(256 * MiB)
-
-#define BDSM		0xb0	/* Base Data Stolen Memory */
-#define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
-#define TOLUD		0xbc	/* Top of Low Used Memory */
-#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
-
-/* IMR registers are found under MCHBAR. */
-#define MCHBAR_IMR0BASE		0x6870
-#define MCHBAR_IMR0MASK		0x6874
-#define MCH_IMR_PITCH		0x20
-#define MCH_NUM_IMRS		20
-
-/* RAPL Package Power Limit register under MCHBAR. */
-#define MCHBAR_RAPL_PPL		0x70A8
-
-#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h
new file mode 100644
index 0000000..f723a80
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/systemagent.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_APOLLOLAKE_SYSTEMAGENT_H
+#define SOC_APOLLOLAKE_SYSTEMAGENT_H
+
+#include <intelblocks/systemagent.h>
+
+#define PCIEX_SIZE	(256 * MiB)
+
+/* IMR registers are found under MCHBAR. */
+#define MCHBAR_IMR0BASE		0x6870
+#define MCHBAR_IMR0MASK		0x6874
+#define MCH_IMR_PITCH		0x20
+#define MCH_NUM_IMRS		20
+
+/* RAPL Package Power Limit register under MCHBAR. */
+#define MCHBAR_RAPL_PPL		0x70A8
+
+#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index cccbffd..7ee8fd7 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -27,7 +27,7 @@
 #include <assert.h>
 #include <cbmem.h>
 #include <device/pci.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/smm.h>
 
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
index 6f92283..62728f5 100644
--- a/src/soc/intel/apollolake/northbridge.c
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -20,7 +20,7 @@
 #include <soc/iomap.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_ids.h>
 
 static uint32_t get_bar(device_t dev, unsigned int index)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 93b571e..b7686db 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -35,7 +35,7 @@
 #include <soc/flash_ctrlr.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
-#include <soc/northbridge.h>
+#include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>