[coreboot-gerrit] Patch set updated for coreboot: cpu/x86: add a barrier with timeout

[Bora Guvendik (bora.guvendik@intel.com)]

Bora Guvendik (bora.guvendik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18107

-gerrit

commit c7d68050b193c45354cc64427930289de080a396
Author: Bora Guvendik <bora.guvendik at intel.com>
Date:   Wed Jan 4 16:51:31 2017 -0800

    cpu/x86: add a barrier with timeout
    
    In case something goes wrong on one of the
    cpus, add the ability to use a barrier with
    timeout so that other cpus don't wait forever.
    Remove static from barrier wait and release.
    
    BUG=chrome-os-partner:59875
    BRANCH=reef
    TEST=None
    
    Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24
    Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
 src/cpu/x86/mp_init.c    | 27 +++++++++++++++++++++++++--
 src/include/cpu/x86/mp.h | 10 ++++++++++
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index c989963..9a3bd4d 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -138,7 +138,7 @@ struct cpu_map {
 /* Keep track of APIC and device structure for each CPU. */
 static struct cpu_map cpus[CONFIG_MAX_CPUS];
 
-static inline void barrier_wait(atomic_t *b)
+inline void barrier_wait(atomic_t *b)
 {
 	while (atomic_read(b) == 0) {
 		asm ("pause");
@@ -146,7 +146,30 @@ static inline void barrier_wait(atomic_t *b)
 	mfence();
 }
 
-static inline void release_barrier(atomic_t *b)
+/* Returns 1 if timeout occurs before barier is released.
+ * returns 0 if barrier is released before timeout. */
+int barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms)
+{
+	int timeout = 0;
+	struct mono_time current, end;
+
+	timer_monotonic_get(&current);
+	end = current;
+	mono_time_add_msecs(&end, timeout_ms);
+
+	while ((atomic_read(b) == 0) && (!mono_time_after(&current, &end))) {
+		timer_monotonic_get(&current);
+		asm ("pause");
+	}
+	mfence();
+
+	if (mono_time_after(&current, &end))
+		timeout = 1;
+
+	return timeout;
+}
+
+inline void release_barrier(atomic_t *b)
 {
 	mfence();
 	atomic_set(b, 1);
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index b9b4d57..0671b62 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -150,5 +150,15 @@ int mp_park_aps(void);
 void smm_initiate_relocation_parallel(void);
 /* Send SMI to self with single execution. */
 void smm_initiate_relocation(void);
+/* Make a CPU wait until the barrier is released */
+void barrier_wait(atomic_t *b);
+/*
+ * Make a CPU wait until the barrier is released, or timeout occurs
+ * returns 1 if timeout occurs before barier is released.
+ * returns 0 if barrier is released before timeout.
+ */
+int barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms);
+/* Release a barrier so that other CPUs waiting for that barrier can continue */
+void release_barrier(atomic_t *b);
 
 #endif /* _X86_MP_H_ */