[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Pass S3 wake status to fsp_silicon_init

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18805

-gerrit

commit c702c0b38f040c3934c74a86b7aa838676a0084c
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Mon Mar 13 17:13:39 2017 -0700

    soc/intel/quark: Pass S3 wake status to fsp_silicon_init
    
    Fix build error with FSP 1.1.  Pass the S3 wake status to
    fsp_silicon_init.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/fsp1_1.c               | 4 ++--
 src/soc/intel/quark/include/soc/ramstage.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c
index ee10e38..1178031 100644
--- a/src/soc/intel/quark/fsp1_1.c
+++ b/src/soc/intel/quark/fsp1_1.c
@@ -17,12 +17,12 @@
 #include <fsp/util.h>
 #include <soc/ramstage.h>
 
-void fsp_silicon_init(void)
+void fsp_silicon_init(bool s3wake)
 {
 	if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
 		intel_silicon_init();
 	else
-		fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+		fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
 }
 
 void soc_silicon_init_params(SILICON_INIT_UPD *upd)
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
index 0ff2128..9187487 100644
--- a/src/soc/intel/quark/include/soc/ramstage.h
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -26,7 +26,7 @@
 
 void mainboard_gpio_i2c_init(device_t dev);
 #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
-void fsp_silicon_init(void);
+void fsp_silicon_init(bool s3wake);
 #endif
 asmlinkage void chipset_teardown_car(void);