[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Read the rmu.bin file from read-only region

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18803

-gerrit

commit 05834c2000e0a4c0aef46676d3244362d16e1670
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Mon Mar 13 16:37:20 2017 -0700

    soc/intel/quark: Read the rmu.bin file from read-only region
    
    Always read the rmu.bin file from the read-only section of the SPI
    flash.  Without this change vboot attempts to read this file from the
    A or B section of the flash.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/include/soc/romstage.h |  1 +
 src/soc/intel/quark/romstage/fsp1_1.c      | 14 ++++++--------
 src/soc/intel/quark/romstage/fsp2_0.c      | 14 ++++++--------
 src/soc/intel/quark/romstage/romstage.c    | 26 ++++++++++++++++++++++++++
 4 files changed, 39 insertions(+), 16 deletions(-)

diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index d6f9186..f015a3d 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -32,6 +32,7 @@
 asmlinkage void *car_stage_c_entry(void);
 void clear_smi_and_wake_events(void);
 void disable_rom_shadow(void);
+char * locate_rmu_file(size_t *rmu_file_len);
 void report_platform_info(void);
 int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
 void pcie_init(void);
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index e93e688..deac3d2 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -17,7 +17,6 @@
 
 #include <arch/early_variables.h>
 #include <console/console.h>
-#include <cbfs.h>
 #include "../chip.h"
 #include <fsp/memmap.h>
 #include <fsp/util.h>
@@ -82,8 +81,8 @@ void soc_memory_init_params(struct romstage_params *params,
 {
 	const struct device *dev;
 	const struct soc_intel_quark_config *config;
-	char *rmu_file;
-	size_t rmu_file_len;
+	char *rmu_data;
+	size_t rmu_data_len;
 
 	/* Locate the configuration data from devicetree.cb */
 	dev = dev_find_slot(0, LPC_DEV_FUNC);
@@ -100,9 +99,8 @@ void soc_memory_init_params(struct romstage_params *params,
 	clear_smi_and_wake_events();
 
 	/* Locate the RMU data file in flash */
-	rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
-		&rmu_file_len);
-	if (!rmu_file)
+	rmu_data = locate_rmu_file(&rmu_data_len);
+	if (!rmu_data)
 		die("Microcode file (rmu.bin) not found.");
 
 	/* Update the UPD data for MemoryInit */
@@ -121,8 +119,8 @@ void soc_memory_init_params(struct romstage_params *params,
 	upd->Flags = config->Flags;
 	upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
 	upd->RankMask = config->RankMask;
-	upd->RmuBaseAddress = (uintptr_t)rmu_file;
-	upd->RmuLength = rmu_file_len;
+	upd->RmuBaseAddress = (uintptr_t)rmu_data;
+	upd->RmuLength = rmu_data_len;
 	upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
 		? (uintptr_t)fsp_write_line : 0;
 	upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 4d7f7c9..538357c 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -15,7 +15,6 @@
 
 #include <arch/early_variables.h>
 #include <console/console.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include "../chip.h"
 #include <cpu/x86/cache.h>
@@ -92,17 +91,16 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
 	FSPM_ARCH_UPD *aupd;
 	const struct device *dev;
 	const struct soc_intel_quark_config *config;
-	char *rmu_file;
-	size_t rmu_file_len;
+	char *rmu_data;
+	size_t rmu_data_len;
 	FSP_M_CONFIG *upd;
 
 	/* Clear SMI and wake events */
 	clear_smi_and_wake_events();
 
 	/* Locate the RMU data file in flash */
-	rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
-		&rmu_file_len);
-	if (!rmu_file)
+	rmu_data = locate_rmu_file(&rmu_data_len);
+	if (!rmu_data)
 		die("Microcode file (rmu.bin) not found.");
 
 	/* Locate the configuration data from devicetree.cb */
@@ -157,8 +155,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
 	upd->Flags = config->Flags;
 	upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
 	upd->RankMask = config->RankMask;
-	upd->RmuBaseAddress = (uintptr_t)rmu_file;
-	upd->RmuLength = rmu_file_len;
+	upd->RmuBaseAddress = (uintptr_t)rmu_data;
+	upd->RmuLength = rmu_data_len;
 	upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
 		? (uintptr_t)fsp_write_line : 0;
 	upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index e774993..e79129e 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -16,6 +16,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/early_variables.h>
+#include <cbfs.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <soc/pci_devs.h>
@@ -61,3 +62,28 @@ void disable_rom_shadow(void)
 			QNC_MSG_FSBIC_REG_HMISC, data);
 	}
 }
+
+char * locate_rmu_file(size_t *rmu_file_len)
+{
+	struct cbfsf fh;
+	size_t fsize;
+	char *rmu_data;
+	uint32_t type;
+
+	/* Locate the rmu.bin file in the read-only region of the flash */
+	type = CBFS_TYPE_RAW;
+	if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type))
+		return NULL;
+
+	/* Get the file size */
+	fsize = region_device_sz(&fh.data);
+	if (rmu_file_len != NULL)
+		*rmu_file_len = fsize;
+
+	/* Get the data address */
+	rmu_data = rdev_mmap(&fh.data, 0, fsize);
+	rdev_munmap(&fh.data, rmu_data);
+
+	/* Return the SPI flash address which can be directly addressed */
+	return rmu_data;
+}