[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake:Add _DSM method to reduce D3 cold delay for eMMC controller

[Zhuo-hao Lee (zhuo-hao.lee@intel.com)]

Zhuo-hao Lee (zhuo-hao.lee at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18806

-gerrit

commit 528273285617eac269665e2e563ccca15f09d80e
Author: Zhuo-hao.Lee <zhuo-hao.lee at intel.com>
Date:   Tue Mar 14 10:27:28 2017 +0800

    soc/intel/apollolake:Add _DSM method to reduce D3 cold delay for eMMC controller
    
    eMMC Controller is taking over 100ms to resume during runtime which
    results in I/O latency issues on the Apollolake systems such as Snappy.
    
    This patch adds _DSM method for eMMC comtroller for specifying the
    device readiness durations. Function index 9 returns package of five
    integers to set D3 cold delay to zero and ACPI constant Ones for the
    elements where overriding the default values is not desired.
    
    BUG=b:35774937
    BRANCH=none
    TEST=update snappy coreboot and test i/o latency is under 100ms
    
    Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee at intel.com>
    Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a
---
 src/soc/intel/apollolake/acpi/scs.asl | 43 +++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
index 05aedca..9ffdfca 100644
--- a/src/soc/intel/apollolake/acpi/scs.asl
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -47,6 +47,49 @@ Scope (\_SB.PCI0) {
 	Device (SDHA) {
 		Name (_ADR, 0x001C0000)
 		Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+		Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
+
+		/*
+		 * Device Specific Method
+		 * Arg0 - UUID
+		 * Arg1 - Revision
+		 * Arg2 - Function Index
+		 */
+		Method (_DSM, 4)
+		{
+			If (LEqual (Arg0, ^UUID)) {
+				/*
+				 * Function 9: Device Readiness Durations
+				 * Returns a package of five integers covering
+				 * various device related delay in PCIe Base Spec.
+				 */
+				If (LEqual (Arg2, 9)) {
+					/*
+					 * Function 9 support for revision 3.
+					 * ECN link for function definitions
+					 * [https://pcisig.com/sites/default/files/
+					 * specification_documents/
+					 * ECN_fw_latency_optimization_final.pdf]
+					 */
+					If (LEqual (Arg1, 3)) {
+						/*
+						 * Integer 0: FW reset time.
+						 * Integer 1: FW data link up time.
+						 * Integer 2: FW functional level reset
+						 * time.
+						 * Integer 3: FW D3 hot to D0 time.
+						 * Integer 4: FW VF enable time.
+						 * set ACPI constant Ones for elements
+						 * where overriding the default value
+						 * is not desired.
+						 */
+						Return (Package (5) {0, Ones, Ones,
+									    Ones, Ones})
+					}
+				}
+			}
+			Return (Buffer() { 0x00 })
+		}
 
 		Method (_PS0, 0, NotSerialized)
 		{