[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Add ESRAM display to FSP 1.1

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18804

-gerrit

commit 8b2b72bf1014f9ab6228b63c725c826ec1eca8c8
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Mon Mar 13 17:03:31 2017 -0700

    soc/intel/quark: Add ESRAM display to FSP 1.1
    
    Ad ESRAM display to FSP 1.1
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/Kconfig           |  1 -
 src/soc/intel/quark/romstage/fsp1_1.c | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 8182caa..c697b56 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -177,7 +177,6 @@ config DCACHE_RAM_SIZE
 config DISPLAY_ESRAM_LAYOUT
 	bool "Display ESRAM layout"
 	default n
-	depends on PLATFORM_USES_FSP2_0
 	help
 	  Select this option to display coreboot's use of ESRAM.
 
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index deac3d2..fca5f26 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -103,6 +103,39 @@ void soc_memory_init_params(struct romstage_params *params,
 	if (!rmu_data)
 		die("Microcode file (rmu.bin) not found.");
 
+	/* Display the ESRAM layout */
+	if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
+		printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
+		printk(BIOS_SPEW,
+			"+-------------------+ 0x80080000 - ESRAM end\n");
+		if (_car_relocatable_data_end != (void *)0x80080000) {
+			printk(BIOS_SPEW, "|                   |\n");
+			printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+				_car_relocatable_data_end);
+		}
+		printk(BIOS_SPEW, "| coreboot data     |\n");
+		printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+			_car_stack_end);
+		printk(BIOS_SPEW, "| coreboot stack    |\n");
+		printk(BIOS_SPEW, "+-------------------+ 0x%p",
+			_car_stack_start);
+		if (IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) {
+			printk(BIOS_SPEW, "\n");
+			printk(BIOS_SPEW, "| vboot data        |\n");
+			printk(BIOS_SPEW, "+-------------------+ 0x%08x",
+				CONFIG_DCACHE_RAM_BASE);
+		}
+		printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n");
+
+		printk(BIOS_SPEW, "| FSP data          |\n");
+		printk(BIOS_SPEW, "+-------------------+\n");
+		printk(BIOS_SPEW, "| FSP stack         |\n");
+		printk(BIOS_SPEW, "+-------------------+\n");
+		printk(BIOS_SPEW, "| FSP binary        |\n");
+		printk(BIOS_SPEW,
+			"+-------------------+ 0x80000000 - ESRAM start\n\n");
+	}
+
 	/* Update the UPD data for MemoryInit */
 	upd->AddrMode = config->AddrMode;
 	upd->ChanMask = config->ChanMask;