[coreboot-gerrit] Patch merged into coreboot/master: mainboard/google/reef: Modify TCPU, TSR2 and TRT table

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 327c5c60ddc14e5f466c7a2f9ac6dcfb4d9f4941
Author: Tim Chen <Tim-Chen at quantatw.com>
Date:   Tue Mar 7 14:45:15 2017 +0800

    mainboard/google/reef: Modify TCPU, TSR2 and TRT table
    
    Update the DPTF parameters based on thermal test result.
    (ZHT_DPTF_EVT2_v0.5_20170306.xlsx)
    
    1. Update DPTF TCPU critical trigger point.
       TCPU critical point: 105
    
    2. Update DPTF TSR2 passive trigger point.
       TSR2 passive point: 58
    
    3. Change thermal relationship table (TRT) setting.
       Change CPU Throttle Effect on CPU sample rate to 10secs.
       Change Charger Effect on Temp Sensor 2 sample rate to 30secs.
       Change CPU Effect on Temp Sensor 2 sample rate to 60secs.
    
    BUG=b:35583586
    BRANCH=master
    TEST=build and boot on electro dut
    
    Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582
    Signed-off-by: Tim Chen <Tim-Chen at quantatw.com>
    Reviewed-on: https://review.coreboot.org/18610
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/18610 for details.

-gerrit