[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/broadwell: Rework IGD's CDClk selection

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e392f414cd27edba78f02a5e9274126aa0a80f89
Author: Nico Huber <nico.h at gmx.de>
Date:   Wed Dec 7 19:29:08 2016 +0100

    soc/intel/broadwell: Rework IGD's CDClk selection
    
    CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
    for Broadwell, never took the devicetree config into account.
    
    Rewrite the selection with the following in mind:
    
      o cpu_is_ult() might return `true` for ULX SKUs, too,
    
      o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
        cooling, so leave that as devicetree option.
    
    For Haswell, the following frequency selections are valid:
    
      o ULX: 337.5MHz by default, 450MHz optional
      o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
                          it wasn't selectable before either)
      o others: 540MHz by default, 450MHz optional
    
    For Broadwell:
    
      o ULX: 450MHz by default, 337.5MHz / 540MHz optional
      o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
      o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional
    
    Side effects: A too high setting in the devicetree results in the
    highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
    instead of 450MHz.
    
    Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
    Signed-off-by: Nico Huber <nico.h at gmx.de>
    Reviewed-on: https://review.coreboot.org/17768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Matt DeVillier <matt.devillier at gmail.com>
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>


See https://review.coreboot.org/17768 for details.

-gerrit