[coreboot-gerrit] Patch set updated for coreboot: device/dram/ddr2: Add functions to select common CAS en freq
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Fri Mar 10 15:19:48 CET 2017
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320
-gerrit
commit e358ca028764f7cf1732c5d68b428f6716118ba5
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Wed Mar 1 20:10:55 2017 +0100
device/dram/ddr2: Add functions to select common CAS en freq
This adds two functions:
- one to find the highest common tCLK per CAS;
- another to find to select tCLK and CAS based on the results of the
previous function and the limits on minimal tCLK the memory controller
can impose.
Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/device/dram/ddr2.c | 77 ++++++++++++++++++++++++++++++++++++++++++
src/include/device/dram/ddr2.h | 5 ++-
2 files changed, 81 insertions(+), 1 deletion(-)
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 1471ed5..e08d1b1 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Patrick Rudolph <siro at das-labor.org>
+ * Copyright (C) 2017 Arthur Heymans <arthur at aheymans.xyz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -628,3 +629,79 @@ void dram_print_spd_ddr2(const struct dimm_attr_st *dimm)
print_us(" tPLL : ", dimm->tPLL);
print_us(" tRR : ", dimm->tRR);
}
+
+/**
+* \Find the common minimal tCLK for all DIMM for each CAS
+*
+* @param cas mask: of supported CAS by all present DIMMs
+* num_dimms: number of DIMMs
+* array of common minimal tCLK per CAS, needs to be of size 8
+* array of minimal tCLK per dimm per CAS, needs to be of size 8
+*/
+
+void get_common_min_tclk(u8 cas_mask, const int num_dimms, u32 *common_min_tclk,
+ u32 **cycle_time)
+{
+ int i, j, high_common_cas;
+
+ high_common_cas = spd_get_msbs(cas_mask);
+ for (i = high_common_cas; cas_mask & (1 << i); i--) {
+ for (j = 0; j < num_dimms; i++) {
+ /* 0 Means that dimm is empty */
+ if(cycle_time[j][i] == 0)
+ continue;
+ common_min_tclk[i] = MAX(common_min_tclk[i],
+ cycle_time[j][i]);
+ }
+ }
+}
+
+/**
+* \Find common tCLK and CAS based on memory controller mimimal tCLK
+* and on common minimal tCLK per CAS
+*
+* @param cas mask: of supported CAS by all present DIMMs
+* array of common minimal tCLK per CAS, needs to be of size 8
+* array of minimal tCLK per dimm per CAS, needs to be of size 8
+* pointer to selected CAS
+* returns: the selected tCLK
+*/
+
+u32 get_common_freq_cas(u8 cas_mask, u32 *common_min_tclk, u8 *selected_cas,
+ u32 mimimum_ctrl_tclk)
+{
+ int high_common_cas;
+ u32 tCLK = 0;
+
+ high_common_cas = spd_get_msbs(cas_mask);
+
+ while (common_min_tclk[high_common_cas] < mimimum_ctrl_tclk) {
+ high_common_cas--;
+ if (high_common_cas < 3)
+ break;
+ }
+
+ tCLK = common_min_tclk[high_common_cas];
+
+ if (tCLK <= TCK_800MHZ) {
+ tCLK = TCK_800MHZ;
+ } else if (tCLK <= TCK_666MHZ) {
+ tCLK = TCK_666MHZ;
+ } else if (tCLK <= TCK_533MHZ) {
+ tCLK = TCK_533MHZ;
+ } else if (tCLK <= TCK_400MHZ) {
+ tCLK = TCK_400MHZ;
+ } else if (tCLK <= TCK_333MHZ) {
+ tCLK = TCK_333MHZ;
+ } else if (tCLK <= TCK_266MHZ) {
+ tCLK = TCK_266MHZ;
+ } else if (tCLK <= TCK_200MHZ) {
+ tCLK = TCK_200MHZ;
+ } else {
+ printk(BIOS_DEBUG, "Too slow common tCLK found\n");
+ return 0;
+ }
+
+ *selected_cas = high_common_cas;
+ return tCLK;
+}
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h
index 7f59a7a..26209e7 100644
--- a/src/include/device/dram/ddr2.h
+++ b/src/include/device/dram/ddr2.h
@@ -213,6 +213,9 @@ u32 spd_decode_spd_size_ddr2(u8 byte0);
u32 spd_decode_eeprom_size_ddr2(u8 byte1);
int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
void dram_print_spd_ddr2(const struct dimm_attr_st *dimm);
-
+void get_common_min_tclk(u8 cas_mask, const int num_dimms, u32 *common_min_tclk,
+ u32 **cycle_time);
+u32 get_common_freq_cas(u8 cas_mask, u32 *common_min_tclk, u8 *selected_cas,
+ u32 mimimum_ctrl_tclk);
#endif /* DEVICE_DRAM_DDR2L_H */
More information about the coreboot-gerrit
mailing list