[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d448a5e98bab6942301032146b5cb0fe5625d496
Author: sowmyav <v.sowmya at intel.com>
Date:   Thu Mar 2 10:09:59 2017 +0530

    soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller
    
    eMMC Controller is taking over 100ms to resume during runtime which
    results in I/O latency issues on the Skylake systems like Cave and Caroline.
    
    This patch adds _DSM method for eMMC comtroller for specifying the
    device readiness durations. Function index 9 returns package of five
    integers to set D3 cold delay to zero and ACPI constant Ones for the
    elements where overriding the default values is not desired.
    
    BUG=b:35774937
    BRANCH=none
    TEST=update caroline coreboot and test i/o latency is under 100ms
    
    Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
    Signed-off-by: Sowmya V <v.sowmya at intel.com>
    Reviewed-on: https://review.coreboot.org/18532
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>


See https://review.coreboot.org/18532 for details.

-gerrit