[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Add PM methods to power gate SD card

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 6dd7b402d512d5bfc5f3bc20b0fc8c80aca817db
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date:   Fri Feb 24 15:37:30 2017 -0800

    soc/intel/apollolake: Add PM methods to power gate SD card
    
    This implements dynamic generation of sdcard GpioInt in SSDT.
    GpioInt in SSDT generation is based on the card detect GPIO if
    it is provided by the mainboard in devicetree.
    
    This implements GNVS variable to store the address of sdcard cd pin.
    GNVS used to store rxstate of the sdcard cd pin to get card presence.
    
    Add _PS0/_PS3 methods to power gate the sd card controller in
    S0ix and runtime PM.
    
    CQ-DEPEND=448173
    BUG=chrome-os-partner:63070
    TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
    System should enter S0ix and resume with no issue.
    
    Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    Reviewed-on: https://review.coreboot.org/18496
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-by: Vaibhav Shankar <vaibhav.shankar at intel.com>


See https://review.coreboot.org/18496 for details.

-gerrit