[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 75d8d8da47a3cc759d7395f5b0ef91ba13a59e51
Author: Li Cheng Sooi <li.cheng.sooi at intel.com>
Date:   Fri Feb 24 02:52:13 2017 +0800

    soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI
    
    Add two GPIO macros:
      1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
         APIC with input assuming the events are edge triggered.
    
      2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
         input to SCI assuming the events are level triggered.
    
    Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
    Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta at intel.com>
    Reviewed-on: https://review.coreboot.org/18533
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/18533 for details.

-gerrit