[coreboot-gerrit] New patch to review for coreboot: southbridge/intel/i82801gx: Fix problems found by checkpatch.pl
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Thu Mar 9 12:03:44 CET 2017
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18705
-gerrit
commit 0de8889ec7867b39ea4888dd7386d0bdb4d2b09b
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Thu Mar 9 12:02:52 2017 +0100
southbridge/intel/i82801gx: Fix problems found by checkpatch.pl
Change-Id: Iddc67e7c126ce19429afc24b021e385353564cb8
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/southbridge/intel/i82801gx/ac97.c | 8 +-
src/southbridge/intel/i82801gx/azalia.c | 7 +-
src/southbridge/intel/i82801gx/early_lpc.c | 6 +-
src/southbridge/intel/i82801gx/early_smbus.c | 5 +-
src/southbridge/intel/i82801gx/i82801gx.h | 14 +-
src/southbridge/intel/i82801gx/ide.c | 3 +-
src/southbridge/intel/i82801gx/lpc.c | 37 ++---
src/southbridge/intel/i82801gx/pci.c | 3 +-
src/southbridge/intel/i82801gx/pcie.c | 9 +-
src/southbridge/intel/i82801gx/sata.c | 9 +-
src/southbridge/intel/i82801gx/smbus.c | 19 +--
src/southbridge/intel/i82801gx/smbus.h | 15 +-
src/southbridge/intel/i82801gx/smi.c | 175 +++++++++++++++--------
src/southbridge/intel/i82801gx/smihandler.c | 204 +++++++++++++++++----------
src/southbridge/intel/i82801gx/usb.c | 3 +-
src/southbridge/intel/i82801gx/usb_ehci.c | 3 +-
16 files changed, 323 insertions(+), 197 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c
index ed800ff..b86891b 100644
--- a/src/southbridge/intel/i82801gx/ac97.c
+++ b/src/southbridge/intel/i82801gx/ac97.c
@@ -96,9 +96,8 @@ static int ac97_semaphore(void)
reg8 = inb(nabmbar + CAS);
timeout--;
} while ((reg8 & 1) && timeout);
- if (! timeout) {
+ if (!timeout)
printk(BIOS_DEBUG, "Timeout!\n");
- }
return (!timeout);
}
@@ -220,7 +219,7 @@ static void ac97_modem_init(struct device *dev)
mbar = pci_read_config16(dev, MBAR) & 0xfffe;
reg16 = inw(mmbar + EXT_MODEM_ID1);
- if ((reg16 & 0xc000) != 0xc000 ) {
+ if ((reg16 & 0xc000) != 0xc000) {
if (reg16 & (1 << 0)) {
reg32 = inw(mmbar + VENDOR_ID2);
reg32 <<= 16;
@@ -247,7 +246,8 @@ static void ac97_modem_init(struct device *dev)
}
}
-static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void ac97_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index b13d809..01c1196 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -87,9 +87,9 @@ no_codec:
return 0;
}
-static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
+static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
{
- int idx=0;
+ int idx = 0;
while (idx < (cim_verb_data_size / sizeof(u32))) {
u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
@@ -303,7 +303,8 @@ static void azalia_init(struct device *dev)
}
}
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 4aa9f10..11da3ec 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -38,15 +38,15 @@ int southbridge_detect_s3_resume(void)
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
+ if (!acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ } else {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
return 1;
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
}
}
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 47fe5f6..93e9d6a 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -29,9 +29,8 @@ void enable_smbus(void)
dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, 0x2) != 0x27da) {
+ if (pci_read_config16(dev, 0x2) != 0x27da)
die("SMBus controller not found!");
- }
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
@@ -51,7 +50,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index d1441e8..9879dfe 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -49,7 +49,7 @@ void i82801gx_enable(device_t dev);
void gpi_route_interrupt(u8 gpi, u8 mode);
#else
void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
int southbridge_detect_s3_resume(void);
#endif
#endif
@@ -200,9 +200,9 @@ int southbridge_detect_s3_resume(void);
/* Root Complex Register Block */
#define RCBA 0xf0
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
+#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
+#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
+#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
@@ -295,9 +295,9 @@ int southbridge_detect_s3_resume(void);
* If UHCI controllers get disabled, EHCI
* must know about it, too! */
#define FD_UHCI4 (1 << 11)
-#define FD_UHCI34 (1 << 10) | FD_UHCI4
-#define FD_UHCI234 (1 << 9) | FD_UHCI3
-#define FD_UHCI1234 (1 << 8) | FD_UHCI2
+#define FD_UHCI34 ((1 << 10) | FD_UHCI4)
+#define FD_UHCI234 ((1 << 9) | FD_UHCI3)
+#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)
#define FD_INTLAN (1 << 7)
#define FD_ACMOD (1 << 6)
diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c
index f82ea17..e135336 100644
--- a/src/southbridge/intel/i82801gx/ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
@@ -91,7 +91,8 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "\n");
}
-static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void ide_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index a995e9f..e650d82 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -109,7 +109,7 @@ static void i82801gx_pirq_init(device_t dev)
*/
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin=0, int_line=0;
+ u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
@@ -117,10 +117,14 @@ static void i82801gx_pirq_init(device_t dev)
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ case 1:
+ /* INTA# */ int_line = config->pirqa_routing; break;
+ case 2:
+ /* INTB# */ int_line = config->pirqb_routing; break;
+ case 3:
+ /* INTC# */ int_line = config->pirqc_routing; break;
+ case 4:
+ /* INTD# */ int_line = config->pirqd_routing; break;
}
if (!int_line)
@@ -168,7 +172,7 @@ static void i82801gx_power_options(device_t dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
@@ -221,7 +225,7 @@ static void i82801gx_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */
} else {
printk(BIOS_INFO, "NMI sources disabled.\n");
- reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
+ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
}
outb(reg8, 0x70);
@@ -321,7 +325,7 @@ static void enable_clock_gating(void)
reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
reg32 |= (1 << 2); // PCIe clock gating;
reg32 &= ~(1 << 20); // No static clock gating for USB
- reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
+ reg32 &= ~((1 << 29) | (1 << 28)); // Disable UHCI clock gating
RCBA32(CG) = reg32;
}
@@ -481,9 +485,9 @@ unsigned long acpi_fill_madt(unsigned long current)
return current;
}
-void acpi_fill_fadt(acpi_fadt_t * fadt)
+void acpi_fill_fadt(acpi_fadt_t *fadt)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
@@ -586,19 +590,17 @@ void acpi_fill_fadt(acpi_fadt_t * fadt)
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
- if (chip->p_cnt_throttling_supported) {
+ if (chip->p_cnt_throttling_supported)
fadt->duty_width = 3;
- } else {
+ else
fadt->duty_width = 0;
- }
fadt->iapc_boot_arch = 0x03;
fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
| ACPI_FADT_C2_MP_SUPPORTED);
- if (chip->docking_supported) {
+ if (chip->docking_supported)
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
- }
}
static void i82801gx_lpc_read_resources(device_t dev)
@@ -643,7 +645,8 @@ static void i82801gx_lpc_read_resources(device_t dev)
}
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -656,7 +659,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index afc275a..03e2544 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -106,7 +106,8 @@ static void ich_pci_bus_enable_resources(struct device *dev)
ich_pci_dev_enable_resources(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 61fc026..0d14ff4 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -89,7 +89,8 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, 0x1e, reg16);
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
@@ -125,7 +126,7 @@ static const unsigned short i82801gx_pcie_ids[] = {
};
static const struct pci_driver i82801gx_pcie __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices= i82801gx_pcie_ids,
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = i82801gx_pcie_ids,
};
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 2fcb83d..a08f266 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -199,7 +199,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, SATA_IR, reg32);
}
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -236,7 +237,7 @@ static const unsigned short sata_ids[] = {
};
static const struct pci_driver i82801gx_sata_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices= sata_ids,
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = sata_ids,
};
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index e6aa018..d028f73 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -38,7 +38,8 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
+static int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
+ unsigned int address, unsigned int data)
{
unsigned char global_status_register;
@@ -92,8 +93,8 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
return do_smbus_write_byte(res->base, device, address, data);
}
-static int do_smbus_block_write(unsigned smbus_base, unsigned device,
- unsigned cmd, unsigned bytes, const u8 *buf)
+static int do_smbus_block_write(unsigned int smbus_base, unsigned int device,
+ unsigned int cmd, unsigned int bytes, const u8 *buf)
{
u8 status;
@@ -123,7 +124,8 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while (!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1))
+ ;
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -155,8 +157,8 @@ static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
-static int do_smbus_block_read(unsigned smbus_base, unsigned device,
- unsigned cmd, unsigned bytes, u8 *buf)
+static int do_smbus_block_read(unsigned int smbus_base, unsigned int device,
+ unsigned int cmd, unsigned int bytes, u8 *buf)
{
u8 status;
int bytes_read = 0;
@@ -180,7 +182,8 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while (!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1))
+ ;
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -225,7 +228,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.block_write = lsmbus_block_write,
};
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(device_t dev, unsigned int vendor, unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801gx/smbus.h b/src/southbridge/intel/i82801gx/smbus.h
index 80456bc..ff8e1fb 100644
--- a/src/southbridge/intel/i82801gx/smbus.h
+++ b/src/southbridge/intel/i82801gx/smbus.h
@@ -24,7 +24,7 @@ static void smbus_delay(void)
static int smbus_wait_until_ready(u16 smbus_base)
{
- unsigned loops = SMBUS_TIMEOUT;
+ unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
@@ -37,7 +37,7 @@ static int smbus_wait_until_ready(u16 smbus_base)
static int smbus_wait_until_done(u16 smbus_base)
{
- unsigned loops = SMBUS_TIMEOUT;
+ unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
@@ -48,14 +48,13 @@ static int smbus_wait_until_done(u16 smbus_base)
return loops ? 0 : -1;
}
-static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+static int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
- if (smbus_wait_until_ready(smbus_base) < 0) {
+ if (smbus_wait_until_ready(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
@@ -77,9 +76,8 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
- if (smbus_wait_until_done(smbus_base) < 0) {
+ if (smbus_wait_until_done(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
global_status_register = inb(smbus_base + SMBHSTSTAT);
@@ -88,8 +86,7 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
/* Read results of transaction */
byte = inb(smbus_base + SMBHSTDAT0);
- if (global_status_register != (1 << 1)) {
+ if (global_status_register != (1 << 1))
return SMBUS_ERROR;
- }
return byte;
}
diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c
index 9dc648f..45fcb10 100644
--- a/src/southbridge/intel/i82801gx/smi.c
+++ b/src/southbridge/intel/i82801gx/smi.c
@@ -57,14 +57,22 @@ static u16 reset_pm1_status(void)
static void dump_pm1_status(u16 pm1_sts)
{
printk(BIOS_DEBUG, "PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
+ if (pm1_sts & (1 << 15))
+ printk(BIOS_DEBUG, "WAK ");
+ if (pm1_sts & (1 << 14))
+ printk(BIOS_DEBUG, "PCIEXPWAK ");
+ if (pm1_sts & (1 << 11))
+ printk(BIOS_DEBUG, "PRBTNOR ");
+ if (pm1_sts & (1 << 10))
+ printk(BIOS_DEBUG, "RTC ");
+ if (pm1_sts & (1 << 8))
+ printk(BIOS_DEBUG, "PWRBTN ");
+ if (pm1_sts & (1 << 5))
+ printk(BIOS_DEBUG, "GBL ");
+ if (pm1_sts & (1 << 4))
+ printk(BIOS_DEBUG, "BM ");
+ if (pm1_sts & (1 << 0))
+ printk(BIOS_DEBUG, "TMROF ");
printk(BIOS_DEBUG, "\n");
}
@@ -86,26 +94,46 @@ static u32 reset_smi_status(void)
static void dump_smi_status(u32 smi_sts)
{
printk(BIOS_DEBUG, "SMI_STS: ");
- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
+ if (smi_sts & (1 << 26))
+ printk(BIOS_DEBUG, "SPI ");
+ if (smi_sts & (1 << 25))
+ printk(BIOS_DEBUG, "EL_SMI ");
+ if (smi_sts & (1 << 21))
+ printk(BIOS_DEBUG, "MONITOR ");
+ if (smi_sts & (1 << 20))
+ printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+ if (smi_sts & (1 << 18))
+ printk(BIOS_DEBUG, "INTEL_USB2 ");
+ if (smi_sts & (1 << 17))
+ printk(BIOS_DEBUG, "LEGACY_USB2 ");
+ if (smi_sts & (1 << 16))
+ printk(BIOS_DEBUG, "SMBUS_SMI ");
+ if (smi_sts & (1 << 15))
+ printk(BIOS_DEBUG, "SERIRQ_SMI ");
+ if (smi_sts & (1 << 14))
+ printk(BIOS_DEBUG, "PERIODIC ");
+ if (smi_sts & (1 << 13))
+ printk(BIOS_DEBUG, "TCO ");
+ if (smi_sts & (1 << 12))
+ printk(BIOS_DEBUG, "DEVMON ");
+ if (smi_sts & (1 << 11))
+ printk(BIOS_DEBUG, "MCSMI ");
+ if (smi_sts & (1 << 10))
+ printk(BIOS_DEBUG, "GPI ");
+ if (smi_sts & (1 << 9))
+ printk(BIOS_DEBUG, "GPE0 ");
+ if (smi_sts & (1 << 8))
+ printk(BIOS_DEBUG, "PM1 ");
+ if (smi_sts & (1 << 6))
+ printk(BIOS_DEBUG, "SWSMI_TMR ");
+ if (smi_sts & (1 << 5))
+ printk(BIOS_DEBUG, "APM ");
+ if (smi_sts & (1 << 4))
+ printk(BIOS_DEBUG, "SLP_SMI ");
+ if (smi_sts & (1 << 3))
+ printk(BIOS_DEBUG, "LEGACY_USB ");
+ if (smi_sts & (1 << 2))
+ printk(BIOS_DEBUG, "BIOS ");
printk(BIOS_DEBUG, "\n");
}
@@ -129,23 +157,38 @@ static void dump_gpe0_status(u32 gpe0_sts)
{
int i;
printk(BIOS_DEBUG, "GPE0_STS: ");
- for (i=31; i>= 16; i--) {
- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+ for (i = 31; i >= 16; i--) {
+ if (gpe0_sts & (1 << i))
+ printk(BIOS_DEBUG, "GPIO%d ", (i-16));
}
- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
+ if (gpe0_sts & (1 << 14))
+ printk(BIOS_DEBUG, "USB4 ");
+ if (gpe0_sts & (1 << 13))
+ printk(BIOS_DEBUG, "PME_B0 ");
+ if (gpe0_sts & (1 << 12))
+ printk(BIOS_DEBUG, "USB3 ");
+ if (gpe0_sts & (1 << 11))
+ printk(BIOS_DEBUG, "PME ");
+ if (gpe0_sts & (1 << 10))
+ printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+ if (gpe0_sts & (1 << 9))
+ printk(BIOS_DEBUG, "PCI_EXP ");
+ if (gpe0_sts & (1 << 8))
+ printk(BIOS_DEBUG, "RI ");
+ if (gpe0_sts & (1 << 7))
+ printk(BIOS_DEBUG, "SMB_WAK ");
+ if (gpe0_sts & (1 << 6))
+ printk(BIOS_DEBUG, "TCO_SCI ");
+ if (gpe0_sts & (1 << 5))
+ printk(BIOS_DEBUG, "AC97 ");
+ if (gpe0_sts & (1 << 4))
+ printk(BIOS_DEBUG, "USB2 ");
+ if (gpe0_sts & (1 << 3))
+ printk(BIOS_DEBUG, "USB1 ");
+ if (gpe0_sts & (1 << 2))
+ printk(BIOS_DEBUG, "HOT_PLUG ");
+ if (gpe0_sts & (1 << 0))
+ printk(BIOS_DEBUG, "THRM ");
printk(BIOS_DEBUG, "\n");
}
@@ -169,8 +212,9 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
{
int i;
printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
- for (i=15; i>= 0; i--) {
- if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
+ for (i = 15; i >= 0; i--) {
+ if (alt_gp_smi_sts & (1 << i))
+ printk(BIOS_DEBUG, "GPI%d ", i);
}
printk(BIOS_DEBUG, "\n");
}
@@ -199,19 +243,32 @@ static u32 reset_tco_status(void)
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
+ if (tco_sts & (1 << 20))
+ printk(BIOS_DEBUG, "SMLINK_SLV ");
+ if (tco_sts & (1 << 18))
+ printk(BIOS_DEBUG, "BOOT ");
+ if (tco_sts & (1 << 17))
+ printk(BIOS_DEBUG, "SECOND_TO ");
+ if (tco_sts & (1 << 16))
+ printk(BIOS_DEBUG, "INTRD_DET ");
+ if (tco_sts & (1 << 12))
+ printk(BIOS_DEBUG, "DMISERR ");
+ if (tco_sts & (1 << 10))
+ printk(BIOS_DEBUG, "DMISMI ");
+ if (tco_sts & (1 << 9))
+ printk(BIOS_DEBUG, "DMISCI ");
+ if (tco_sts & (1 << 8))
+ printk(BIOS_DEBUG, "BIOSWR ");
+ if (tco_sts & (1 << 7))
+ printk(BIOS_DEBUG, "NEWCENTURY ");
+ if (tco_sts & (1 << 3))
+ printk(BIOS_DEBUG, "TIMEOUT ");
+ if (tco_sts & (1 << 2))
+ printk(BIOS_DEBUG, "TCO_INT ");
+ if (tco_sts & (1 << 1))
+ printk(BIOS_DEBUG, "SW_TCO ");
+ if (tco_sts & (1 << 0))
+ printk(BIOS_DEBUG, "NMI2SMI ");
printk(BIOS_DEBUG, "\n");
}
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 2c21ea7..6bd9517 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -99,14 +99,22 @@ static u16 reset_pm1_status(void)
static void dump_pm1_status(u16 pm1_sts)
{
printk(BIOS_SPEW, "PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
- if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
- if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
- if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
- if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
- if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
+ if (pm1_sts & (1 << 15))
+ printk(BIOS_SPEW, "WAK ");
+ if (pm1_sts & (1 << 14))
+ printk(BIOS_SPEW, "PCIEXPWAK ");
+ if (pm1_sts & (1 << 11))
+ printk(BIOS_SPEW, "PRBTNOR ");
+ if (pm1_sts & (1 << 10))
+ printk(BIOS_SPEW, "RTC ");
+ if (pm1_sts & (1 << 8))
+ printk(BIOS_SPEW, "PWRBTN ");
+ if (pm1_sts & (1 << 5))
+ printk(BIOS_SPEW, "GBL ");
+ if (pm1_sts & (1 << 4))
+ printk(BIOS_SPEW, "BM ");
+ if (pm1_sts & (1 << 0))
+ printk(BIOS_SPEW, "TMROF ");
printk(BIOS_SPEW, "\n");
int reg16 = inw(pmbase + PM1_EN);
printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
@@ -130,26 +138,46 @@ static u32 reset_smi_status(void)
static void dump_smi_status(u32 smi_sts)
{
printk(BIOS_DEBUG, "SMI_STS: ");
- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
+ if (smi_sts & (1 << 26))
+ printk(BIOS_DEBUG, "SPI ");
+ if (smi_sts & (1 << 25))
+ printk(BIOS_DEBUG, "EL_SMI ");
+ if (smi_sts & (1 << 21))
+ printk(BIOS_DEBUG, "MONITOR ");
+ if (smi_sts & (1 << 20))
+ printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+ if (smi_sts & (1 << 18))
+ printk(BIOS_DEBUG, "INTEL_USB2 ");
+ if (smi_sts & (1 << 17))
+ printk(BIOS_DEBUG, "LEGACY_USB2 ");
+ if (smi_sts & (1 << 16))
+ printk(BIOS_DEBUG, "SMBUS_SMI ");
+ if (smi_sts & (1 << 15))
+ printk(BIOS_DEBUG, "SERIRQ_SMI ");
+ if (smi_sts & (1 << 14))
+ printk(BIOS_DEBUG, "PERIODIC ");
+ if (smi_sts & (1 << 13))
+ printk(BIOS_DEBUG, "TCO ");
+ if (smi_sts & (1 << 12))
+ printk(BIOS_DEBUG, "DEVMON ");
+ if (smi_sts & (1 << 11))
+ printk(BIOS_DEBUG, "MCSMI ");
+ if (smi_sts & (1 << 10))
+ printk(BIOS_DEBUG, "GPI ");
+ if (smi_sts & (1 << 9))
+ printk(BIOS_DEBUG, "GPE0 ");
+ if (smi_sts & (1 << 8))
+ printk(BIOS_DEBUG, "PM1 ");
+ if (smi_sts & (1 << 6))
+ printk(BIOS_DEBUG, "SWSMI_TMR ");
+ if (smi_sts & (1 << 5))
+ printk(BIOS_DEBUG, "APM ");
+ if (smi_sts & (1 << 4))
+ printk(BIOS_DEBUG, "SLP_SMI ");
+ if (smi_sts & (1 << 3))
+ printk(BIOS_DEBUG, "LEGACY_USB ");
+ if (smi_sts & (1 << 2))
+ printk(BIOS_DEBUG, "BIOS ");
printk(BIOS_DEBUG, "\n");
}
@@ -173,23 +201,38 @@ static void dump_gpe0_status(u32 gpe0_sts)
{
int i;
printk(BIOS_DEBUG, "GPE0_STS: ");
- for (i=31; i>= 16; i--) {
- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+ for (i = 31; i >= 16; i--) {
+ if (gpe0_sts & (1 << i))
+ printk(BIOS_DEBUG, "GPIO%d ", (i-16));
}
- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
+ if (gpe0_sts & (1 << 14))
+ printk(BIOS_DEBUG, "USB4 ");
+ if (gpe0_sts & (1 << 13))
+ printk(BIOS_DEBUG, "PME_B0 ");
+ if (gpe0_sts & (1 << 12))
+ printk(BIOS_DEBUG, "USB3 ");
+ if (gpe0_sts & (1 << 11))
+ printk(BIOS_DEBUG, "PME ");
+ if (gpe0_sts & (1 << 10))
+ printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+ if (gpe0_sts & (1 << 9))
+ printk(BIOS_DEBUG, "PCI_EXP ");
+ if (gpe0_sts & (1 << 8))
+ printk(BIOS_DEBUG, "RI ");
+ if (gpe0_sts & (1 << 7))
+ printk(BIOS_DEBUG, "SMB_WAK ");
+ if (gpe0_sts & (1 << 6))
+ printk(BIOS_DEBUG, "TCO_SCI ");
+ if (gpe0_sts & (1 << 5))
+ printk(BIOS_DEBUG, "AC97 ");
+ if (gpe0_sts & (1 << 4))
+ printk(BIOS_DEBUG, "USB2 ");
+ if (gpe0_sts & (1 << 3))
+ printk(BIOS_DEBUG, "USB1 ");
+ if (gpe0_sts & (1 << 2))
+ printk(BIOS_DEBUG, "HOT_PLUG ");
+ if (gpe0_sts & (1 << 0))
+ printk(BIOS_DEBUG, "THRM ");
printk(BIOS_DEBUG, "\n");
}
@@ -215,19 +258,32 @@ static u32 reset_tco_status(void)
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
+ if (tco_sts & (1 << 20))
+ printk(BIOS_DEBUG, "SMLINK_SLV ");
+ if (tco_sts & (1 << 18))
+ printk(BIOS_DEBUG, "BOOT ");
+ if (tco_sts & (1 << 17))
+ printk(BIOS_DEBUG, "SECOND_TO ");
+ if (tco_sts & (1 << 16))
+ printk(BIOS_DEBUG, "INTRD_DET ");
+ if (tco_sts & (1 << 12))
+ printk(BIOS_DEBUG, "DMISERR ");
+ if (tco_sts & (1 << 10))
+ printk(BIOS_DEBUG, "DMISMI ");
+ if (tco_sts & (1 << 9))
+ printk(BIOS_DEBUG, "DMISCI ");
+ if (tco_sts & (1 << 8))
+ printk(BIOS_DEBUG, "BIOSWR ");
+ if (tco_sts & (1 << 7))
+ printk(BIOS_DEBUG, "NEWCENTURY ");
+ if (tco_sts & (1 << 3))
+ printk(BIOS_DEBUG, "TIMEOUT ");
+ if (tco_sts & (1 << 2))
+ printk(BIOS_DEBUG, "TCO_INT ");
+ if (tco_sts & (1 << 1))
+ printk(BIOS_DEBUG, "SW_TCO ");
+ if (tco_sts & (1 << 0))
+ printk(BIOS_DEBUG, "NMI2SMI ");
printk(BIOS_DEBUG, "\n");
}
@@ -325,14 +381,17 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
*/
switch (slp_typ) {
- case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
- case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+ case ACPI_S0:
+ printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+ case ACPI_S1:
+ printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
- case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+ case ACPI_S4:
+ printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
@@ -342,17 +401,17 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- if (s5pwr == MAINBOARD_POWER_ON) {
+ if (s5pwr == MAINBOARD_POWER_ON)
reg8 &= ~1;
- } else {
+ else
reg8 |= 1;
- }
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
break;
- default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
+ default:
+ printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
}
#if !CONFIG_SMM_TSEG
@@ -360,7 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
* will never be unlocked because the next outl will switch off the CPU.
* This might open a small race between the smi_release_lock() and the outl()
* for other SMI handlers. Not sure if this could cause trouble. */
- if (slp_typ == ACPI_S3)
+ if (slp_typ == ACPI_S3)
smi_release_lock();
#endif
@@ -481,7 +540,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
mainboard_smi_gpi(reg16);
if (reg16)
- printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
+ printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
}
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
@@ -509,7 +568,8 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
if (!tco_sts)
return;
- if (tco_sts & (1 << 8)) { // BIOSWR
+ if (tco_sts & (1 << 8)) {
+ /* BIOSWR */
u8 bios_cntl;
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
@@ -560,7 +620,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
trap_cycle = RCBA32(0x1e10);
- for (i=16; i<20; i++) {
+ for (i = 16; i < 20; i++) {
if (trap_cycle & (1 << i))
mask |= (0xff << ((i - 16) << 2));
}
@@ -579,7 +639,9 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
/* IOTRAP(0) SMIC: currently unused */
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i = 0; i < 4; i++)
+ if (IOTRAP(i))
+ printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
@@ -666,8 +728,6 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
- if (dump) {
+ if (dump)
dump_smi_status(smi_sts);
- }
-
}
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c
index 4e852e2..2978080 100644
--- a/src/southbridge/intel/i82801gx/usb.c
+++ b/src/southbridge/intel/i82801gx/usb.c
@@ -42,7 +42,8 @@ static void usb_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index 8735ba5..6ed2dcb 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -58,7 +58,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;
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