[coreboot-gerrit] Patch set updated for coreboot: src/include: Add parenthesis around macros
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Wed Mar 8 20:06:14 CET 2017
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18649
-gerrit
commit 8e92e2ce5b9a201d097b595cbb47e64501f470a5
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Tue Mar 7 13:17:49 2017 -0800
src/include: Add parenthesis around macros
Fix the following error found by checkpatch.pl:
ERROR: Macros with complex values should be enclosed in parentheses
False positives are detected for attribute macros. An example is:
ERROR: Macros with complex values should be enclosed in parentheses
+#define BOOT_STATE_INIT_ATTR __attribute__ ((used, section
(".bs_init")))
False positive also generated for macros for linker script files. An
example is:
ERROR: Macros with complex values should be enclosed in parentheses
+#define CBFS_CACHE(addr, size) \
+ REGION(cbfs_cache, addr, size, 4) \
+ ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \
+ ALIAS_REGION(cbfs_cache, postram_cbfs_cache)
False positives generated for assembly code macros. An example is:
ERROR: Macros with complex values should be enclosed in parentheses
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name
)
False positive detected when macro includes multiple comma separated
values. The following code is from src/include/device/azalia_device.h:
#define AZALIA_SUBVENDOR(codec, val) \
(((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \
(((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
(((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
(((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))
TEST=Build and run on Galileo Gen2
Change-Id: I6e3b6950738e6906851a172ba3a22e3d5af1e35d
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
src/include/console/cbmem_console.h | 4 ++--
src/include/console/spi.h | 4 ++--
src/include/console/uart.h | 4 ++--
src/include/console/usb.h | 4 ++--
src/include/cpu/amd/gx2def.h | 8 ++++----
src/include/cpu/amd/lxdef.h | 2 +-
src/include/cpu/amd/sc520.h | 6 +++---
src/include/device/azalia_device.h | 16 ++++++++--------
src/include/device/pci_rom.h | 2 +-
src/include/watchdog.h | 2 +-
10 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
index de1144b..f8b3982 100644
--- a/src/include/console/cbmem_console.h
+++ b/src/include/console/cbmem_console.h
@@ -21,11 +21,11 @@
void cbmemc_init(void);
void cbmemc_tx_byte(unsigned char data);
-#define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \
+#define __CBMEM_CONSOLE_ENABLE__ (CONFIG_CONSOLE_CBMEM && \
(ENV_RAMSTAGE || ENV_VERSTAGE || ENV_POSTCAR || \
(IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) && \
(ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE)))\
- )
+ ))
#if __CBMEM_CONSOLE_ENABLE__
static inline void __cbmemc_init(void) { cbmemc_init(); }
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
index bf58a36..32741fb 100644
--- a/src/include/console/spi.h
+++ b/src/include/console/spi.h
@@ -22,8 +22,8 @@
void spiconsole_init(void);
void spiconsole_tx_byte(unsigned char c);
-#define __CONSOLE_SPI_ENABLE__ CONFIG_SPI_CONSOLE && \
- (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI))
+#define __CONSOLE_SPI_ENABLE__ (CONFIG_SPI_CONSOLE && \
+ (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)))
#if __CONSOLE_SPI_ENABLE__
static inline void __spiconsole_init(void) { spiconsole_init(); }
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index ffcc088..2c745dd 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -55,9 +55,9 @@ static inline void *uart_platform_baseptr(int idx)
void oxford_remap(unsigned int new_base);
-#define __CONSOLE_SERIAL_ENABLE__ CONFIG_CONSOLE_SERIAL && \
+#define __CONSOLE_SERIAL_ENABLE__ (CONFIG_CONSOLE_SERIAL && \
(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \
- ENV_POSTCAR || (ENV_SMM && CONFIG_DEBUG_SMI))
+ ENV_POSTCAR || (ENV_SMM && CONFIG_DEBUG_SMI)))
#if __CONSOLE_SERIAL_ENABLE__
static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); }
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
index b758c03..d52ea87 100644
--- a/src/include/console/usb.h
+++ b/src/include/console/usb.h
@@ -27,8 +27,8 @@ void usb_tx_flush(int idx);
unsigned char usb_rx_byte(int idx);
int usb_can_rx_byte(int idx);
-#define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \
- ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE)
+#define __CONSOLE_USB_ENABLE__ (CONFIG_CONSOLE_USB && \
+ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE))
#define USB_PIPE_FOR_CONSOLE 0
#define USB_PIPE_FOR_GDB 0
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index beb4c65..60db369 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -78,7 +78,7 @@
#define GL1_PCI 4
#define GL1_FG 5
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
+#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx - To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
@@ -86,9 +86,9 @@
#define MSR_GP (GL0_GP << 29) /* A000xxxx */
#define MSR_DF (GL0_DF << 29) /* C000xxxx */
-#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
-#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
-#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
+#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
+#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
+#define MSR_FG ((GL1_FG << 26) + MSR_GLIU1) /* 5400xxxx */
/* GeodeLink Interface Unit 0 (GLIU0) port0 */
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 19b1efa..4865bea 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -59,7 +59,7 @@
#define GL1_AES 6
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
+#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx, To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
diff --git a/src/include/cpu/amd/sc520.h b/src/include/cpu/amd/sc520.h
index 53a62b5..4e748be 100644
--- a/src/include/cpu/amd/sc520.h
+++ b/src/include/cpu/amd/sc520.h
@@ -10,11 +10,11 @@ struct parreg {
unsigned long reg[16];
};
-#define PARREG (struct parreg *)0xfffef088
+#define PARREG ((struct parreg *)0xfffef088)
//static volatile struct parreg *par = PARREG;
-#define MMCRPIC (struct mmcrpic *) 0xfffefd00
+#define MMCRPIC ((struct mmcrpic *) 0xfffefd00)
//static volatile struct mmcrpic *pic = MMCRPIC;
#define M_GINT_MODE 1
@@ -308,4 +308,4 @@ struct mmcr {
};
-#define MMCRDEFAULT (struct mmcr *) 0xfffef000
+#define MMCRDEFAULT ((struct mmcr *) 0xfffef000)
diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h
index e1cbafe..6aedf4b 100644
--- a/src/include/device/azalia_device.h
+++ b/src/include/device/azalia_device.h
@@ -37,15 +37,15 @@ extern const u32 pc_beep_verbs_size;
const u32 cim_verb_data_size = sizeof(cim_verb_data)
#define AZALIA_PIN_CFG(codec, pin, val) \
- ((codec) << 28) | ((pin) << 20) | ( 0x71c << 8) | ((val) & 0xff), \
- ((codec) << 28) | ((pin) << 20) | ( 0x71d << 8) | (((val) >> 8) & 0xff), \
- ((codec) << 28) | ((pin) << 20) | ( 0x71e << 8) | (((val) >> 16) & 0xff), \
- ((codec) << 28) | ((pin) << 20) | ( 0x71f << 8) | (((val) >> 24) & 0xff)
+ (((codec) << 28) | ((pin) << 20) | ( 0x71c << 8) | ((val) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | ( 0x71d << 8) | (((val) >> 8) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | ( 0x71e << 8) | (((val) >> 16) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | ( 0x71f << 8) | (((val) >> 24) & 0xff))
#define AZALIA_SUBVENDOR(codec, val) \
- ((codec) << 28) | (0x01720 << 8) | ((val) & 0xff), \
- ((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff), \
- ((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff), \
- ((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff)
+ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \
+ (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
+ (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
+ (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))
#endif /* DEVICE_AZALIA_H */
diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h
index 3f09778..decd806 100644
--- a/src/include/device/pci_rom.h
+++ b/src/include/device/pci_rom.h
@@ -5,7 +5,7 @@
#include <arch/acpi.h>
#define PCI_ROM_HDR 0xAA55
-#define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' )
+#define PCI_DATA_HDR ((uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ))
#define PCI_RAM_IMAGE_START 0xD0000
#define PCI_VGA_RAM_IMAGE_START 0xC0000
diff --git a/src/include/watchdog.h b/src/include/watchdog.h
index 8514158..375563d 100644
--- a/src/include/watchdog.h
+++ b/src/include/watchdog.h
@@ -4,7 +4,7 @@
#if CONFIG_USE_WATCHDOG_ON_BOOT
void watchdog_off(void);
#else
-#define watchdog_off() while (0) {}
+#define watchdog_off() { while (0); }
#endif
#endif /* WATCHDOG_H */
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