[coreboot-gerrit] New patch to review for coreboot: src/include: Add space after +

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18650

-gerrit

commit 6e883ee9ec49befd9b34160f14ebcf1c27dd8a43
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Tue Mar 7 14:20:56 2017 -0800

    src/include: Add space after +
    
    Fix the following error detected by checkpatch.py:
    
    ERROR: need consistent spacing around '+' (ctx:WxV)
    
    Test: Build and run on Galileo Gen2
    
    Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3
    Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
 src/include/cpu/amd/gx2def.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index 60db369..2904857 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -288,7 +288,7 @@
 
 #define	GLCP_DELAY_CONTROLS		(MSR_GLCP + 0x0F)
 
-#define	GLCP_SYS_RSTPLL				(MSR_GLCP +0x14	/* R/W */)
+#define	GLCP_SYS_RSTPLL				(MSR_GLCP + 0x14 /* R/W */)
 #define		RSTPLL_UPPER_MDIV_SHIFT		9
 #define		RSTPLL_UPPER_VDIV_SHIFT		6
 #define		RSTPLL_UPPER_FBDIV_SHIFT	0