[coreboot-gerrit] New patch to review for coreboot: AGESA: Move amd_initmmio() call

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18623

-gerrit

commit 0232bd6e1950cdb0ebf36370ebd9bead8bdedb9d
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Nov 21 07:37:13 2016 +0200

    AGESA: Move amd_initmmio() call
    
    Function enables PCI MMCONF and XIP cache, it needs
    to be called before giving platform any chance of
    calling any PCI access functions.
    
    Change-Id: Ic044d4df7b93667fa987c29c810d0bd826af87ad
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/agesa/cache_as_ram.inc      | 9 +++++++--
 src/cpu/amd/agesa/family12/romstage.c   | 6 +++++-
 src/cpu/amd/agesa/family14/romstage.c   | 7 +++++--
 src/cpu/amd/agesa/family15/romstage.c   | 7 +++++--
 src/cpu/amd/agesa/family15rl/romstage.c | 7 +++++--
 src/cpu/amd/agesa/family15tn/romstage.c | 7 +++++--
 src/cpu/amd/agesa/family16kb/romstage.c | 7 +++++--
 src/include/cpu/amd/car.h               | 2 ++
 8 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index b316670..03346e4 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -108,19 +108,24 @@ cache_as_ram_setup:
   # use call far to switch to 64-bit code segment
   ljmp $0x18, $1f
 1:
+
+  .code64
+
+  call early_all_cores
+
   /* Pass the cpu_init_detected */
   cvtsd2si        %xmm1, %esi
 
   /* Pass the BIST result */
   cvtsd2si        %xmm0, %edi
 
-
-  .code64
   call    cache_as_ram_main
   .code32
 
 #else
 
+  call early_all_cores
+
   /* Restore the BIST result */
   cvtsd2si  %xmm0, %edx
 
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
index add119f..6c52f99 100644
--- a/src/cpu/amd/agesa/family12/romstage.c
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -34,13 +34,17 @@
 #include <arch/cpu.h>
 #include "platform_cfg.h"
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
 	post_code(0x35);
-	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c
index fe87d18..cd7a092 100644
--- a/src/cpu/amd/agesa/family14/romstage.c
+++ b/src/cpu/amd/agesa/family14/romstage.c
@@ -38,13 +38,16 @@
 #include <cpu/amd/car.h>
 #include <sb_cimx.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		sb_Poweron_Init();
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
index b783c4a..cd799bd 100644
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -29,13 +29,16 @@
 #include <nb_cimx.h>
 #include <sb_cimx.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	post_code(0x30);
-	amd_initmmio();
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
index b4c2ee2..39b4045 100644
--- a/src/cpu/amd/agesa/family15rl/romstage.c
+++ b/src/cpu/amd/agesa/family15rl/romstage.c
@@ -32,13 +32,16 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		board_BeforeAgesa(cb);
diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c
index 2be6ad3..985f9cb 100644
--- a/src/cpu/amd/agesa/family15tn/romstage.c
+++ b/src/cpu/amd/agesa/family15tn/romstage.c
@@ -33,13 +33,16 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 
diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c
index 406dc5b..ed3a18c 100644
--- a/src/cpu/amd/agesa/family16kb/romstage.c
+++ b/src/cpu/amd/agesa/family16kb/romstage.c
@@ -32,13 +32,16 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
+void asmlinkage early_all_cores(void)
+{
+	amd_initmmio();
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sysinfo *cb = NULL;
 	u32 val;
 
-	amd_initmmio();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index a9c9aa0..7fd83f1 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -16,4 +16,6 @@ void cache_as_ram_new_stack(void);
 void disable_cache_as_ram(void);
 #endif
 
+void asmlinkage early_all_cores(void);
+
 #endif