[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller

[V Sowmya (v.sowmya@intel.com)]

V Sowmya (v.sowmya at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18532

-gerrit

commit 45805ded71dd25e118745fe6ee5065fc6dabfc33
Author: sowmyav <v.sowmya at intel.com>
Date:   Thu Mar 2 10:09:59 2017 +0530

    soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller
    
    eMMC Controller is taking over 100ms to resume during runtime which
    results in I/O latency issues on the Skylake systems like Cave and Caroline.
    
    This patch adds _DSM method for eMMC comtroller for specifying the
    device readiness durations. Function index 9 returns package of five
    integers to set D3 cold delay to zero and ACPI constant Ones for the
    elements where overriding the default values is not desired.
    
    BUG: buganizer-35774937
    BRANCH: none
    TEST: update caroline coreboot and test i/o latency is under 100ms
    
    Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
    Signed-off-by: Sowmya V <v.sowmya at intel.com>
---
 src/soc/intel/skylake/acpi/scs.asl | 42 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
index aea4483..204a213 100644
--- a/src/soc/intel/skylake/acpi/scs.asl
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -20,6 +20,7 @@ Device (EMMC)
 {
 	Name (_ADR, 0x001E0004)
 	Name (_DDN, "eMMC Controller")
+	Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
 
 	OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
 	Field (EMCR, DWordAcc, NoLock, Preserve)
@@ -30,6 +31,47 @@ Device (EMMC)
 		, 2,
 		PGEN, 1,	/* PG_ENABLE */
 	}
+	/*
+	 * Device Specific Method
+	 * Arg0 - UUID
+	 * Arg1 - Revision
+	 * Arg2 - Function Index
+	*/
+        Method (_DSM, 4)
+	{
+		If (LEqual (Arg0, ^UUID)) {
+			/*
+			 * Function 9: Device Readiness Durations
+			 * Returns a package of five integers covering
+			 * various device related delay in PCIe Base Spec.
+			*/
+			If (LEqual (Arg2, 9)) {
+				/*
+				 * Function 9 support for revision 3.
+				 * ECN link for function definitions
+				 * [https://pcisig.com/sites/default/files/
+				 * specification_documents/
+				 * ECN_fw_latency_optimization_final.pdf]
+				*/
+				If (LEqual (Arg1, 3)) {
+					/*
+					 * Integer 0: FW reset time.
+					 * Integer 1: FW data link up time.
+					 * Integer 2: FW functional level reset
+					 * time.
+					 * Integer 3: FW D3 hot to D0 time.
+					 * Integer 4: FW VF enable time.
+					 * set ACPI constant Ones for elements
+					 * where overriding the default value
+					 * is not desired.
+					*/
+					Return (package (5) {0, Ones, Ones,
+								    Ones, Ones})
+				}
+			}
+		}
+		Return (Buffer() { 0x00 })
+	}
 
 	Method (_PS0, 0, Serialized)
 	{