[coreboot-gerrit] New patch to review for coreboot: src/include: Fix most errors detected with checkpatch
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue Mar 7 02:11:24 CET 2017
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18605
-gerrit
commit c909d2b82a1ea220bef974c2411fe2543e821df2
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Mon Mar 6 11:34:14 2017 -0800
src/include: Fix most errors detected with checkpatch
Fix most of the errors detected with checkpatch.py and fix the code
impacted by these changes. The primary ripple is caused by removing
semicolons from the end of the macros.
The following errors and warnings were not fixed:
The following files were skipped (too many errors):
* src/include/amd/vr.h
* src/include/memlayout.h
ERROR: Macros with complex values should be enclosed in parentheses
+#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \
+ bscb_->location = BOOT_STATE_CALLBACK_LOC
ERROR: Macros with complex values should be enclosed in parentheses
+#define BOOT_STATE_INIT_ATTR __attribute__ ((used,
section(".bs_init")))
ERROR: Macros with complex values should be enclosed in parentheses
+#define BOOT_STATE_INIT_ATTR __attribute__ ((unused))
ERROR: Macros with complex values should be enclosed in parentheses
#13: FILE: src/include/cpu/cpu.h:13:
+#define __cpu_driver __attribute__ ((used,
__section__(".rodata.cpu_driver")))
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#6: FILE: src/include/cpu/x86/post_code.h:6:
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $CONFIG_POST_IO_PORT
ERROR: need consistent spacing around '%' (ctx:WxV)
#7: FILE: src/include/cpu/x86/post_code.h:7:
+ movb $value, %al; \
^
ERROR: need consistent spacing around '%' (ctx:WxV)
#8: FILE: src/include/cpu/x86/post_code.h:8:
+ outb %al, $CONFIG_POST_IO_PORT
^
ERROR: Macros with complex values should be enclosed in parentheses
#40: FILE: src/include/device/azalia_device.h:40:
+#define AZALIA_PIN_CFG(codec, pin, val)
\
+ (((codec) << 28) | ((pin) << 20) | (0x71c << 8)
\
+ | ((val) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | (0x71d << 8)
\
+ | (((val) >> 8) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | (0x71e << 8)
\
+ | (((val) >> 16) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | (0x71f << 8)
\
+ | (((val) >> 24) & 0xff))
ERROR: Macros with complex values should be enclosed in parentheses
#50: FILE: src/include/device/azalia_device.h:50:
+#define AZALIA_SUBVENDOR(codec, val)
\
+ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)),
\
+ (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)),
\
+ (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)),
\
+ (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))
ERROR: Macros with complex values should be enclosed in parentheses
#60: FILE: src/include/device/pci.h:60:
+#define __pci_driver __attribute__ ((used,
__section__(".rodata.pci_driver")))
ERROR: Macros with complex values should be enclosed in parentheses
#110: FILE: src/include/reg_script.h:110:
+#define REG_SCRIPT_TABLE_ATTRIBUTE \
+ __attribute__ ((used, section(".rsbe_init")))
ERROR: Macros with complex values should be enclosed in parentheses
#114: FILE: src/include/symbols.h:114:
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e"
#name)
ERROR: Macros with complex values should be enclosed in parentheses
#40: FILE: src/include/trace.h:40:
+#define DISABLE_TRACE_ON_FUNCTION __attribute__
((no_instrument_function))
WARNING: storage class should be at the beginning of the declaration
#118: FILE: src/include/cbmem.h:118:
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t
\
WARNING: storage class should be at the beginning of the declaration
#124: FILE: src/include/cbmem.h:124:
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t
\
WARNING: macros should not use a trailing semicolon
#135: FILE: src/include/cbmem.h:135:
+#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((used, \
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t
\
+ init_fn_ ## _ptr_ = init_fn_;
WARNING: storage class should be at the beginning of the declaration
#136: FILE: src/include/cbmem.h:136:
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t
\
WARNING: storage class should be at the beginning of the declaration
#60: FILE: src/include/cpu/amd/common/cbtypes.h:60:
+#define STATIC static
WARNING: storage class should be at the beginning of the declaration
#516: FILE: src/include/cpu/x86/smm.h:516:
+typedef asmlinkage void (*smm_handler_t)(void *);
WARNING: storage class should be at the beginning of the declaration
#34: FILE: src/include/stddef.h:34:
+#define MAYBE_STATIC static
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: I627960b9ff73bf2ac202abec15ce64f52576f1c3
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
src/arch/x86/gdt.c | 2 +-
src/cpu/x86/car.c | 2 +-
src/include/assert.h | 6 +-
src/include/bootblock_common.h | 4 +-
src/include/bootstate.h | 18 +--
src/include/cbfs.h | 3 +-
src/include/cbmem.h | 57 +++++----
src/include/console/cbmem_console.h | 4 +-
src/include/console/console.h | 6 +-
src/include/console/early_print.h | 28 +++--
src/include/console/ne2k.h | 15 ++-
src/include/console/post_codes.h | 12 +-
src/include/console/qemu_debugcon.h | 5 +-
src/include/console/spi.h | 9 +-
src/include/console/uart.h | 41 +++++--
src/include/console/usb.h | 19 ++-
src/include/console/vtxprintf.h | 4 +-
src/include/cpu/amd/amdfam10_sysconf.h | 57 ++++-----
src/include/cpu/amd/amdk8_sysconf.h | 18 +--
src/include/cpu/amd/gx2def.h | 62 ++++++----
src/include/cpu/amd/lxdef.h | 154 ++++++++++++++-----------
src/include/cpu/amd/model_fxx_rev.h | 18 +--
src/include/cpu/amd/msr.h | 3 +-
src/include/cpu/amd/mtrr.h | 5 +-
src/include/cpu/amd/powernow.h | 5 +-
src/include/cpu/amd/sc520.h | 8 +-
src/include/cpu/cpu.h | 4 +-
src/include/cpu/intel/l2_cache.h | 8 +-
src/include/cpu/intel/romstage.h | 4 +-
src/include/cpu/x86/cr.h | 8 +-
src/include/cpu/x86/lapic.h | 54 +++++----
src/include/cpu/x86/mp.h | 2 +-
src/include/cpu/x86/msr.h | 26 ++---
src/include/cpu/x86/mtrr.h | 30 ++---
src/include/cpu/x86/smm.h | 10 +-
src/include/cpu/x86/tsc.h | 4 +-
src/include/delay.h | 6 +-
src/include/device/azalia.h | 10 +-
src/include/device/azalia_device.h | 29 +++--
src/include/device/device.h | 70 ++++++-----
src/include/device/dram/ddr3.h | 40 +++----
src/include/device/hypertransport_def.h | 6 +-
src/include/device/i2c.h | 53 +++++----
src/include/device/path.h | 69 +++++------
src/include/device/pci.h | 53 +++++----
src/include/device/pci_ehci.h | 4 +-
src/include/device/pci_ids.h | 4 +-
src/include/device/pci_rom.h | 5 +-
src/include/device/pnp.h | 4 +-
src/include/device/resource.h | 45 +++++---
src/include/device/smbus.h | 40 +++----
src/include/ip_checksum.h | 3 +-
src/include/memrange.h | 29 ++---
src/include/nhlt.h | 3 +-
src/include/pc80/i8259.h | 2 +-
src/include/pc80/mc146818rtc.h | 18 +--
src/include/reg_script.h | 9 +-
src/include/rmodule.h | 4 +-
src/include/rtc.h | 3 +-
src/include/sdram_mode.h | 2 +-
src/include/smbios.h | 9 +-
src/include/smp/atomic.h | 2 +-
src/include/spd.h | 127 ++++++++++++--------
src/include/spd_ddr2.h | 28 +++--
src/include/stdlib.h | 4 +-
src/include/string.h | 13 ++-
src/include/swab.h | 12 +-
src/include/symbols.h | 2 +-
src/include/thread.h | 13 ++-
src/include/timer.h | 6 +-
src/include/timestamp.h | 3 +-
src/include/tpm_lite/tlcl.h | 6 +-
src/include/tpm_lite/tss_constants.h | 5 +-
src/include/trace.h | 10 +-
src/include/vbe.h | 8 +-
src/include/watchdog.h | 2 +-
src/lib/cbmem_console.c | 6 +-
src/lib/ext_stage_cache.c | 6 +-
src/lib/timestamp.c | 4 +-
src/soc/intel/broadwell/romstage/power_state.c | 2 +-
src/soc/intel/skylake/romstage/power_state.c | 2 +-
src/vboot/common.c | 2 +-
src/vboot/vboot_handoff.c | 2 +-
src/vendorcode/google/chromeos/cros_vpd.c | 2 +-
84 files changed, 850 insertions(+), 652 deletions(-)
diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c
index f662edd..16fdbda 100644
--- a/src/arch/x86/gdt.c
+++ b/src/arch/x86/gdt.c
@@ -59,4 +59,4 @@ static void move_gdt(int is_recovery)
__asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
printk(BIOS_DEBUG, "ok\n");
}
-RAMSTAGE_CBMEM_INIT_HOOK(move_gdt)
+RAMSTAGE_CBMEM_INIT_HOOK(move_gdt);
diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c
index f9b427a..21a16ed 100644
--- a/src/cpu/x86/car.c
+++ b/src/cpu/x86/car.c
@@ -140,4 +140,4 @@ static void car_migrate_variables(int is_recovery)
if (!IS_ENABLED(PLATFORM_USES_FSP1_0))
do_car_migrate_variables();
}
-ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables)
+ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables);
diff --git a/src/include/assert.h b/src/include/assert.h
index 1985389..90cc2a8 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -24,13 +24,15 @@
if (!(x)) { \
printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \
", line %d\n", __FILE__, __LINE__); \
- if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) hlt(); \
+ if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) \
+ hlt(); \
} \
}
#define BUG() { \
printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\
", line %d\n", __FILE__, __LINE__); \
- if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) hlt(); \
+ if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) \
+ hlt(); \
}
#define assert(statement) ASSERT(statement)
diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h
index 04fc0cb..6ede77c 100644
--- a/src/include/bootblock_common.h
+++ b/src/include/bootblock_common.h
@@ -33,7 +33,7 @@ void bootblock_soc_init(void);
/*
* C code entry point for the boot block.
*/
-void asmlinkage bootblock_c_entry(uint64_t base_timestamp);
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp);
/*
* This is a the same as the bootblock main(), with the difference that it does
@@ -43,6 +43,6 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp);
* This function assumes that the timer has already been initialized, so it
* does not call init_timer().
*/
-void asmlinkage bootblock_main_with_timestamp(uint64_t base_timestamp);
+asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp);
#endif /* __BOOTBLOCK_COMMON_H */
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 481a8bc..b7b53d3 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -125,7 +125,7 @@ struct boot_state_callback {
#define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__)
#define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC,
#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \
- bscb_->location = BOOT_STATE_CALLBACK_LOC;
+ bscb_->location = BOOT_STATE_CALLBACK_LOC
#else
#define BOOT_STATE_CALLBACK_INIT_DEBUG
#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_)
@@ -144,18 +144,20 @@ struct boot_state_callback {
/* Initialize an allocated boot_state_callback. */
#define INIT_BOOT_STATE_CALLBACK(bscb_, func_, arg_) \
- INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \
- bscb_->callback = func_; \
- bscb_->arg = arg_
+ do { \
+ INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_); \
+ bscb_->callback = func_; \
+ bscb_->arg = arg_; \
+ } while {0}
/* The following 2 functions schedule a callback to be called on entry/exit
* to a given state. Note that there are no ordering guarantees between the
* individual callbacks on a given state. 0 is returned on success < 0 on
* error. */
int boot_state_sched_on_entry(struct boot_state_callback *bscb,
- boot_state_t state);
+ boot_state_t state);
int boot_state_sched_on_exit(struct boot_state_callback *bscb,
- boot_state_t state);
+ boot_state_t state);
/* Schedule an array of entries of size num. */
struct boot_state_init_entry;
void boot_state_sched_entries(struct boot_state_init_entry *entries,
@@ -179,7 +181,7 @@ struct boot_state_init_entry {
};
#if ENV_RAMSTAGE
-#define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init")))
+#define BOOT_STATE_INIT_ATTR __attribute__ ((used, section(".bs_init")))
#else
#define BOOT_STATE_INIT_ATTR __attribute__ ((unused))
#endif
@@ -193,7 +195,7 @@ struct boot_state_init_entry {
}; \
static struct boot_state_init_entry * \
bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \
- & func_ ##_## state_ ##_## when_;
+ &func_ ##_## state_ ##_## when_
/* Hook per arch when coreboot is exiting to payload or ACPI OS resume. It's
* the very last thing done before the transition. */
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 1350671..c7c7822 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -50,7 +50,8 @@ size_t cbfs_boot_load_struct(const char *name, void *buf, size_t buf_size);
size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset,
size_t in_size, void *buffer, size_t buffer_size, uint32_t compression);
-/* Return the size and fill base of the memory pstage will occupy after loaded. */
+/* Return the size and fill base of the memory pstage will occupy after loaded.
+ */
size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base);
/* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index c13fe92..c42fbe2 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -52,7 +52,7 @@ struct cbmem_entry;
/* Determine the size for CBMEM root and the small allocations */
static inline size_t cbmem_overhead_size(void)
{
- return 2 * CBMEM_ROOT_MIN_SIZE;
+ return 2 * CBMEM_ROOT_MIN_SIZE;
}
/* By default cbmem is attempted to be recovered. Returns 0 if cbmem was
@@ -112,39 +112,38 @@ void cbmem_list(void);
void cbmem_add_records_to_cbtable(struct lb_header *header);
#if ENV_RAMSTAGE
-#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused_ __attribute__((unused)) = init_fn_;
-#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \
- static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \
- section(".rodata.cbmem_init_hooks"))) = init_fn_;
-#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused2_ __attribute__((unused)) = init_fn_;
+#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused_ = init_fn_
+#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((used, \
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t \
+ init_fn_ ## _ptr_ = init_fn_
+#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused2_ = init_fn_
#elif ENV_ROMSTAGE
-#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \
- static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \
- section(".rodata.cbmem_init_hooks"))) = init_fn_;
-#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused_ __attribute__((unused)) = init_fn_;
-#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused2_ __attribute__((unused)) = init_fn_;
+#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((used, \
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t \
+ init_fn_ ## _ptr_ = init_fn_
+#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused_ = init_fn_
+#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused2_ = init_fn_
#elif ENV_POSTCAR
-#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused2_ __attribute__((unused)) = init_fn_;
-#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused_ __attribute__((unused)) = init_fn_;
-#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) \
- static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \
- section(".rodata.cbmem_init_hooks"))) = init_fn_;
+#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused2_ = init_fn_
+#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused_ = init_fn_
+#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((used, \
+ section(".rodata.cbmem_init_hooks"))) static cbmem_init_hook_t \
+ init_fn_ ## _ptr_ = init_fn_
#else
-#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused_ __attribute__((unused)) = init_fn_;
-#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused2_ __attribute__((unused)) = init_fn_;
-#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \
- init_fn_ ## _unused3_ __attribute__((unused)) = init_fn_;
+#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused_ = init_fn_
+#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused2_ = init_fn_
+#define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
+ static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_
#endif /* ENV_RAMSTAGE */
-
/* These are for compatibility with old boards only. Any new chipset and board
* must implement cbmem_top() for both romstage and ramstage to support
* early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE.
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
index de1144b..f8b3982 100644
--- a/src/include/console/cbmem_console.h
+++ b/src/include/console/cbmem_console.h
@@ -21,11 +21,11 @@
void cbmemc_init(void);
void cbmemc_tx_byte(unsigned char data);
-#define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \
+#define __CBMEM_CONSOLE_ENABLE__ (CONFIG_CONSOLE_CBMEM && \
(ENV_RAMSTAGE || ENV_VERSTAGE || ENV_POSTCAR || \
(IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) && \
(ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE)))\
- )
+ ))
#if __CBMEM_CONSOLE_ENABLE__
static inline void __cbmemc_init(void) { cbmemc_init(); }
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 013ef20..6a80a47 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -48,11 +48,11 @@ void __attribute__ ((noreturn)) die(const char *msg);
#if __CONSOLE_ENABLE__
asmlinkage void console_init(void);
int console_log_level(int msg_level);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
+int do_printk(int msg_level, const char *fmt, ...)
+ __attribute__((format(printf, 2, 3)));
void do_putchar(unsigned char byte);
-#define printk(LEVEL, fmt, args...) \
- do { do_printk(LEVEL, fmt, ##args); } while (0)
+#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args)
#else
static inline void console_init(void) {}
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index bd12500..29e9f21 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -25,21 +25,27 @@
/* While in romstage, console loglevel is built-time constant.
* With ROMCC we inline this test with help from preprocessor.
*/
-#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level)
+#define console_log_level(msg_level) \
+ (msg_level <= CONFIG_DEFAULT_CONSOLE_LOGLEVEL)
-#define CALL_CONSOLE_TX(loglevel, tx_func, x) \
- do { \
- if (console_log_level(loglevel)) { \
- tx_func(x); \
+#define CALL_CONSOLE_TX(loglevel, tx_func, x) \
+ do { \
+ if (console_log_level(loglevel)) { \
+ tx_func(x); \
console_tx_flush(); \
- } \
+ } \
} while (0)
-#define __console_tx_char(level, x) CALL_CONSOLE_TX(level, console_tx_byte, x)
-#define __console_tx_hex8(level, x) CALL_CONSOLE_TX(level, console_tx_hex8, x)
-#define __console_tx_hex16(level, x) CALL_CONSOLE_TX(level, console_tx_hex16, x)
-#define __console_tx_hex32(level, x) CALL_CONSOLE_TX(level, console_tx_hex32, x)
-#define __console_tx_string(level, x) CALL_CONSOLE_TX(level, console_tx_string, x)
+#define __console_tx_char(level, x) \
+ CALL_CONSOLE_TX(level, console_tx_byte, x)
+#define __console_tx_hex8(level, x) \
+ CALL_CONSOLE_TX(level, console_tx_hex8, x)
+#define __console_tx_hex16(level, x) \
+ CALL_CONSOLE_TX(level, console_tx_hex16, x)
+#define __console_tx_hex32(level, x) \
+ CALL_CONSOLE_TX(level, console_tx_hex32, x)
+#define __console_tx_string(level, x) \
+ CALL_CONSOLE_TX(level, console_tx_string, x)
#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR)
#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR)
diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h
index d7974b5..ea2a139 100644
--- a/src/include/console/ne2k.h
+++ b/src/include/console/ne2k.h
@@ -28,9 +28,18 @@ void ne2k_transmit(unsigned int eth_nic_base);
#endif
#if CONFIG_CONSOLE_NE2K && (ENV_ROMSTAGE || ENV_RAMSTAGE)
-static inline void __ne2k_init(void) { ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); }
-static inline void __ne2k_tx_byte(u8 data) { ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); }
-static inline void __ne2k_tx_flush(void) { ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); }
+static inline void __ne2k_init(void)
+{
+ ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
+}
+static inline void __ne2k_tx_byte(u8 data)
+{
+ ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT);
+}
+static inline void __ne2k_tx_flush(void)
+{
+ ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT);
+}
#else
static inline void __ne2k_init(void) {}
static inline void __ne2k_tx_byte(u8 data) {}
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 9f24199..a396325 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -63,7 +63,7 @@
*
* POSTed before ramstage is about to be loaded into memory
*/
-#define POST_PREPARE_RAMSTAGE 0x11
+#define POST_PREPARE_RAMSTAGE 0x11
/**
* \brief Copy/decompression finished; jumping to RAM
@@ -341,18 +341,20 @@
* \n
* Check the console output to see exactly where the failure occurred.
*/
-#define POST_DIE 0xff
+#define POST_DIE 0xff
/*
* The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
* They overlap with previous codes, and most are not even used
- * Some mainboards still require them, but they are deprecated. We want to consolidate
- * our own POST code structure with the codes above.
+ * Some mainboards still require them, but they are deprecated. We want to
+ * consolidate our own POST code structure with the codes above.
*
* standard AMD post definitions for the AMD Geode
*/
-#define POST_Output_Port (0x080) /* port to write post codes to*/
+
+/* port to write post codes to*/
+#define POST_Output_Port (0x080)
#define POST_preSioInit (0x000)
#define POST_clockInit (0x001)
diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h
index 257ae58..544442a 100644
--- a/src/include/console/qemu_debugcon.h
+++ b/src/include/console/qemu_debugcon.h
@@ -9,7 +9,10 @@ void qemu_debugcon_tx_byte(unsigned char data);
#if CONFIG_CONSOLE_QEMU_DEBUGCON && (ENV_ROMSTAGE || ENV_RAMSTAGE)
static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); }
-static inline void __qemu_debugcon_tx_byte(u8 data) { qemu_debugcon_tx_byte(data); }
+static inline void __qemu_debugcon_tx_byte(u8 data)
+{
+ qemu_debugcon_tx_byte(data);
+}
#else
static inline void __qemu_debugcon_init(void) {}
static inline void __qemu_debugcon_tx_byte(u8 data) {}
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
index bf58a36..4d281ac 100644
--- a/src/include/console/spi.h
+++ b/src/include/console/spi.h
@@ -22,12 +22,15 @@
void spiconsole_init(void);
void spiconsole_tx_byte(unsigned char c);
-#define __CONSOLE_SPI_ENABLE__ CONFIG_SPI_CONSOLE && \
- (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI))
+#define __CONSOLE_SPI_ENABLE__ (CONFIG_SPI_CONSOLE && \
+ (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)))
#if __CONSOLE_SPI_ENABLE__
static inline void __spiconsole_init(void) { spiconsole_init(); }
-static inline void __spiconsole_tx_byte(u8 data) { spiconsole_tx_byte(data); }
+static inline void __spiconsole_tx_byte(u8 data)
+{
+ spiconsole_tx_byte(data);
+}
#else
static inline void __spiconsole_init(void) {}
static inline void __spiconsole_tx_byte(u8 data) {}
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index ffcc088..204469b 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -55,14 +55,23 @@ static inline void *uart_platform_baseptr(int idx)
void oxford_remap(unsigned int new_base);
-#define __CONSOLE_SERIAL_ENABLE__ CONFIG_CONSOLE_SERIAL && \
+#define __CONSOLE_SERIAL_ENABLE__ (CONFIG_CONSOLE_SERIAL && \
(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \
- ENV_POSTCAR || (ENV_SMM && CONFIG_DEBUG_SMI))
+ ENV_POSTCAR || (ENV_SMM && CONFIG_DEBUG_SMI)))
#if __CONSOLE_SERIAL_ENABLE__
-static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); }
-static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); }
-static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); }
+static inline void __uart_init(void)
+{
+ uart_init(CONFIG_UART_FOR_CONSOLE);
+}
+static inline void __uart_tx_byte(u8 data)
+{
+ uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data);
+}
+static inline void __uart_tx_flush(void)
+{
+ uart_tx_flush(CONFIG_UART_FOR_CONSOLE);
+}
#else
static inline void __uart_init(void) {}
static inline void __uart_tx_byte(u8 data) {}
@@ -70,11 +79,23 @@ static inline void __uart_tx_flush(void) {}
#endif
#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE)
-#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE
-static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); }
-static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); }
-static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); }
-static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); }
+#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE
+static inline void __gdb_hw_init(void)
+{
+ uart_init(CONFIG_UART_FOR_GDB);
+}
+static inline void __gdb_tx_byte(u8 data)
+{
+ uart_tx_byte(CONFIG_UART_FOR_GDB, data);
+}
+static inline void __gdb_tx_flush(void)
+{
+ uart_tx_flush(CONFIG_UART_FOR_GDB);
+}
+static inline u8 __gdb_rx_byte(void)
+{
+ return uart_rx_byte(CONFIG_UART_FOR_GDB);
+}
#endif
#endif /* __ROMCC__ */
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
index b758c03..aa5198d 100644
--- a/src/include/console/usb.h
+++ b/src/include/console/usb.h
@@ -27,16 +27,25 @@ void usb_tx_flush(int idx);
unsigned char usb_rx_byte(int idx);
int usb_can_rx_byte(int idx);
-#define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \
- ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE)
+#define __CONSOLE_USB_ENABLE__ (CONFIG_CONSOLE_USB && \
+ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE))
#define USB_PIPE_FOR_CONSOLE 0
#define USB_PIPE_FOR_GDB 0
#if __CONSOLE_USB_ENABLE__
-static inline void __usbdebug_init(void) { usbdebug_init(); }
-static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); }
-static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); }
+static inline void __usbdebug_init(void)
+{
+ usbdebug_init();
+}
+static inline void __usb_tx_byte(u8 data)
+{
+ usb_tx_byte(USB_PIPE_FOR_CONSOLE, data);
+}
+static inline void __usb_tx_flush(void)
+{
+ usb_tx_flush(USB_PIPE_FOR_CONSOLE);
+}
#else
static inline void __usbdebug_init(void) {}
static inline void __usb_tx_byte(u8 data) {}
diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h
index 3336198..ebef4378 100644
--- a/src/include/console/vtxprintf.h
+++ b/src/include/console/vtxprintf.h
@@ -22,9 +22,9 @@
* On LLVM we can still just include stdarg.h.
*/
#ifdef __GNUC__
-#define va_start(v,l) __builtin_va_start(v,l)
+#define va_start(v, l) __builtin_va_start(v, l)
#define va_end(v) __builtin_va_end(v)
-#define va_arg(v,l) __builtin_va_arg(v,l)
+#define va_arg(v, l) __builtin_va_arg(v, l)
typedef __builtin_va_list va_list;
#else
#include <stdarg.h>
diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h
index ade78c8..2ae654e 100644
--- a/src/include/cpu/amd/amdfam10_sysconf.h
+++ b/src/include/cpu/amd/amdfam10_sysconf.h
@@ -21,41 +21,44 @@
#include <cpu/x86/msr.h>
struct p_state_t {
- unsigned corefreq;
- unsigned power;
- unsigned transition_lat;
- unsigned busmaster_lat;
- unsigned control;
- unsigned status;
+ unsigned int corefreq;
+ unsigned int power;
+ unsigned int transition_lat;
+ unsigned int busmaster_lat;
+ unsigned int control;
+ unsigned int status;
};
struct amdfam10_sysconf_t {
//ht
- unsigned hc_possible_num;
- unsigned pci1234[HC_POSSIBLE_NUM];
- unsigned hcdn[HC_POSSIBLE_NUM];
- unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type
- unsigned sbdn;
- unsigned sblk;
+ unsigned int hc_possible_num;
+ unsigned int pci1234[HC_POSSIBLE_NUM];
+ unsigned int hcdn[HC_POSSIBLE_NUM];
+ unsigned int hcid[HC_POSSIBLE_NUM]; //record ht chain type
+ unsigned int sbdn;
+ unsigned int sblk;
- unsigned nodes;
- unsigned ht_c_num; // we only can have 32 ht chain at most
- unsigned ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
- unsigned io_addr_num;
- unsigned conf_io_addr[HC_NUMS];
- unsigned conf_io_addrx[HC_NUMS];
- unsigned mmio_addr_num;
- unsigned conf_mmio_addr[HC_NUMS*2]; // mem and pref mem
- unsigned conf_mmio_addrx[HC_NUMS*2];
- unsigned segbit;
- unsigned hcdn_reg[HC_NUMS]; // it will be used by get_pci1234
+ unsigned int nodes;
+ unsigned int ht_c_num; // we only can have 32 ht chain at most
+ unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max,
+ // 8:bus_min, 4:linkn,
+ // 6: nodeid, 2: enable
+ unsigned int io_addr_num;
+ unsigned int conf_io_addr[HC_NUMS];
+ unsigned int conf_io_addrx[HC_NUMS];
+ unsigned int mmio_addr_num;
+ unsigned int conf_mmio_addr[HC_NUMS*2]; // mem and pref mem
+ unsigned int conf_mmio_addrx[HC_NUMS*2];
+ unsigned int segbit;
+ unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234
- msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5
- unsigned needs_update_pstate_msrs;
+ msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node
+ // should be the same, and p0,..p5
+ unsigned int needs_update_pstate_msrs;
- unsigned bsp_apicid;
+ unsigned int bsp_apicid;
int enabled_apic_ext_id;
- unsigned lift_bsp_apicid;
+ unsigned int lift_bsp_apicid;
int apicid_offset;
void *mb; // pointer for mb related struct
diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h
index 87bd4d5..665f9f9 100644
--- a/src/include/cpu/amd/amdk8_sysconf.h
+++ b/src/include/cpu/amd/amdk8_sysconf.h
@@ -5,18 +5,18 @@
struct amdk8_sysconf_t {
//ht
- unsigned nodes;
- unsigned hc_possible_num;
- unsigned pci1234[HC_POSSIBLE_NUM];
- unsigned hcdn[HC_POSSIBLE_NUM];
- unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type
- unsigned sbdn;
- unsigned sblk;
+ unsigned int nodes;
+ unsigned int hc_possible_num;
+ unsigned int pci1234[HC_POSSIBLE_NUM];
+ unsigned int hcdn[HC_POSSIBLE_NUM];
+ unsigned int hcid[HC_POSSIBLE_NUM]; //record ht chain type
+ unsigned int sbdn;
+ unsigned int sblk;
- unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234
+ unsigned int hcdn_reg[4]; // it will be used by get_sblk_pci1234
int enabled_apic_ext_id;
- unsigned lift_bsp_apicid;
+ unsigned int lift_bsp_apicid;
int apicid_offset;
void *mb; // pointer for mb related struct
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index beb4c65..8a6e0c7 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -32,7 +32,7 @@
/* GLCP_SYS_RSTPLL, Lower 32 bits */
#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
-#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
+#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
#define GLCP_SYS_RSTPLL_LOCKWAIT 24
#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
#define GLCP_SYS_RSTPLL_BYPASS 15
@@ -78,17 +78,21 @@
#define GL1_PCI 4
#define GL1_FG 5
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
+/* 1000xxxx - To get on GeodeLink one bit has to be set */
+#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28))
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
-#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
+/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't
+ * need to be routed
+ */
+#define MSR_CPU (GL0_CPU << 29)
#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
#define MSR_GP (GL0_GP << 29) /* A000xxxx */
#define MSR_DF (GL0_DF << 29) /* C000xxxx */
-#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
-#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
-#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
+#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
+#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
+#define MSR_FG ((GL1_FG << 26) + MSR_GLIU1) /* 5400xxxx */
/* GeodeLink Interface Unit 0 (GLIU0) port0 */
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
@@ -288,12 +292,12 @@
#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
-#define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */)
+#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14 /* R/W */)
#define RSTPLL_UPPER_MDIV_SHIFT 9
#define RSTPLL_UPPER_VDIV_SHIFT 6
#define RSTPLL_UPPER_FBDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
-#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
+#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
#define RSTPPL_LOWER_BYPASS_SHIFT 15
#define RSTPPL_LOWER_TST_SHIFT 11
@@ -392,15 +396,23 @@
#define MAX_COL_ADDR 17
/* more fun stuff */
-#define BM 1 /* Base Mask - map power of 2 size aligned region */
+/* Base Mask - map power of 2 size aligned region */
+#define BM 1
#define BMO 2 /* BM with an offset */
#define R 3 /* Range - 4k range minimum */
#define RO 4 /* R with offset */
-#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
+/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
+#define SC 5
#define BMIO 6 /* Base Mask IO */
#define SCIO 7 /* Swiss 0xCeese IO */
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */
+/* Special marker for Shadow SC descriptors so setShadow proc is independent
+ * of CPU
+ */
+#define SC_SHADOW 8
+#define R_SYSMEM 9
+/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent
+ * of CPU
+ */
#define BMO_SMM 10 /* Special marker for SMM */
#define BM_SMM 11 /* Special marker for SMM */
#define BMO_DMM 12 /* Special marker for DMM */
@@ -417,13 +429,13 @@
//remove after MSRINIT is gone
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */
-#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
-#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */
+#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
+#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */
#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */
#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */
-#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */
-#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */
+#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */
+#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */
#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */
#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */
@@ -484,20 +496,26 @@
/* definitions that are "once you are mostly up, start VSA" type things */
#define SMM_OFFSET 0x40400000
-#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
+/* changed SMM_SIZE from 256 KB to 128 KB */
+#define SMM_SIZE 128
#define DMM_OFFSET 0x0C0000000
#define DMM_SIZE 128
#define FB_OFFSET 0x41000000
-#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
-#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
-#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
+/* Top of PCI mem allocation region */
+#define PCI_MEM_TOP 0x0EFFFFFFF
+/* Top of PCI I/O allocation region */
+#define PCI_IO_TOP 0x0EFFF
+/* E0000 is reserved for SystemROMs */
+#define END_OPTIONROM_SPACE 0x0DFFF
#define MDD_SMBUS 0x06000 /* SMBUS IO location */
#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
-#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
+/* General Purpose Timers IO location */
+#define MDD_MFGPT 0x06200
#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
#define ACPI_BASE 0x09C00 /* ACPI Base */
-#define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */
+/* Power Management Logic - placed at the end of ACPI */
+#define MDD_PM 0x09D00
#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
#define CHIPSET_DEV_NUM 15
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 19b1efa..430a148 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -21,7 +21,8 @@
#ifndef CPU_AMD_LXDEF_H
#define CPU_AMD_LXDEF_H
-#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/
+/* Stepping ID 1.x CPUbug fix to change it to 5A0*/
+#define CPU_ID_1_X 0x00000560
#define CPU_ID_2_0 0x000005A1
#define CPU_ID_3_0 0x000005A2
@@ -32,7 +33,8 @@
#define CPU_REV_2_2 0x022
#define CPU_REV_C_0 0x030
#define CPU_REV_C_1 0x031
-#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/
+/* 3.2 part was never produced ...*/
+#define CPU_REV_C_2 0x032
#define CPU_REV_C_3 0x033
@@ -59,19 +61,23 @@
#define GL1_AES 6
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
+/* 1000xxxx, To get on GeodeLink one bit has to be set */
+#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28))
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
-#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
+/* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need
+ * to be routed
+ */
+#define MSR_CPU (GL0_CPU << 29)
#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
#define MSR_GP (GL0_GP << 29) /* A000xxxx */
-#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
-#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
-#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
-#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
-#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
-#define MSR_FG MSR_GLCP
+#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
+#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
+#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
+#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
+#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
+#define MSR_FG MSR_GLCP
/*GeodeLink Interface Unit 0 (GLIU0) port0*/
@@ -162,32 +168,32 @@
/* CPU ; does not need routing instructions since we are executing there.*/
-#define CPU_GLD_MSR_CAP 0x2000
-#define CPU_GLD_MSR_CONFIG 0x2001
-#define CPU_GLD_MSR_PM 0x2004
+#define CPU_GLD_MSR_CAP 0x2000
+#define CPU_GLD_MSR_CONFIG 0x2001
+#define CPU_GLD_MSR_PM 0x2004
-#define CPU_GLD_MSR_DIAG 0x2005
-#define DIAG_SEL1_MODE_SHIFT 16
-#define DIAG_SEL1_SET (1 << 31)
-#define DIAG_SEL0__MODE_SHIFT 0
-#define DIAG_SET0_SET (1 << 15)
+#define CPU_GLD_MSR_DIAG 0x2005
+#define DIAG_SEL1_MODE_SHIFT 16
+#define DIAG_SEL1_SET (1 << 31)
+#define DIAG_SEL0__MODE_SHIFT 0
+#define DIAG_SET0_SET (1 << 15)
-#define CPU_PF_CONF 0x1100
-#define RETURN_STACK_ENABLE_SET (1 << 4)
-#define PF_CONF_CC_L1 (1 << 0)
-#define CPU_PF_INVD 0x1102
-#define PF_RS_INVD_SET (1 << 1)
-#define PF_CC_INVD_SET (1 << 0)
-#define CPU_PF_BIST 0x1140
+#define CPU_PF_CONF 0x1100
+#define RETURN_STACK_ENABLE_SET (1 << 4)
+#define PF_CONF_CC_L1 (1 << 0)
+#define CPU_PF_INVD 0x1102
+#define PF_RS_INVD_SET (1 << 1)
+#define PF_CC_INVD_SET (1 << 0)
+#define CPU_PF_BIST 0x1140
-#define CPU_XC_CONFIG 0x1210
-#define XC_CONFIG_SUSP_ON_HLT (1 << 0)
-#define XC_CONFIG_SUSP_ON_PAUSE (1 << 1)
+#define CPU_XC_CONFIG 0x1210
+#define XC_CONFIG_SUSP_ON_HLT (1 << 0)
+#define XC_CONFIG_SUSP_ON_PAUSE (1 << 1)
-#define CPU_ID_CONFIG 0x1250
-#define ID_CONFIG_SERIAL_SET (1 << 0)
+#define CPU_ID_CONFIG 0x1250
+#define ID_CONFIG_SERIAL_SET (1 << 0)
-#define CPU_AC_MSR 0x1301
+#define CPU_AC_MSR 0x1301
/* SMM*/
#define CPU_AC_SMM_CTL 0x1301
@@ -198,26 +204,26 @@
#define INTL_SMI_EN_SET (1 << 4)
#define EXTL_SMI_EN_SET (1 << 5)
-#define CPU_EX_BIST 0x1428
+#define CPU_EX_BIST 0x1428
/*IM*/
-#define CPU_IM_CONFIG 0x1700
-#define IM_CONFIG_LOWER_SERIAL_SET (1 << 2)
-#define IM_CONFIG_LOWER_L0WE_SET (1 << 6)
-#define IM_CONFIG_LOWER_ICD_SET (1 << 8)
-#define IM_CONFIG_LOWER_EBE_SET (1 << 10)
-#define IM_CONFIG_LOWER_ABSE_SET (1 << 11)
-#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
-#define CPU_IC_INDEX 0x1710
-#define CPU_IC_DATA 0x1711
-#define CPU_IC_TAG 0x1712
-#define CPU_IC_TAG_I 0x1713
-#define CPU_ITB_INDEX 0x1720
-#define CPU_ITB_LRU 0x1721
-#define CPU_ITB_ENTRY 0x1722
-#define CPU_ITB_ENTRY_I 0x1723
-#define CPU_IM_BIST_TAG 0x1730
-#define CPU_IM_BIST_DATA 0x1731
+#define CPU_IM_CONFIG 0x1700
+#define IM_CONFIG_LOWER_SERIAL_SET (1 << 2)
+#define IM_CONFIG_LOWER_L0WE_SET (1 << 6)
+#define IM_CONFIG_LOWER_ICD_SET (1 << 8)
+#define IM_CONFIG_LOWER_EBE_SET (1 << 10)
+#define IM_CONFIG_LOWER_ABSE_SET (1 << 11)
+#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
+#define CPU_IC_INDEX 0x1710
+#define CPU_IC_DATA 0x1711
+#define CPU_IC_TAG 0x1712
+#define CPU_IC_TAG_I 0x1713
+#define CPU_ITB_INDEX 0x1720
+#define CPU_ITB_LRU 0x1721
+#define CPU_ITB_ENTRY 0x1722
+#define CPU_ITB_ENTRY_I 0x1723
+#define CPU_IM_BIST_TAG 0x1730
+#define CPU_IM_BIST_DATA 0x1731
/*DM MSR MAP*/
@@ -313,7 +319,7 @@
#define CPU_BC_MSS_ARRAY_CTL2 0x1983
#define CPU_FPU_MSR_MODE 0x1A00
-#define FPU_IE_SET (1 << 0)
+#define FPU_IE_SET (1 << 0)
#define CPU_FP_UROM_BIST 0x1A03
@@ -386,13 +392,15 @@
#define RSTPLL_UPPER_CPUMULT_SHIFT 1
#define RSTPLL_UPPER_CPUDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
-#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
+#define RSTPLL_LOWER_SWFLAGS_MASK \
+ (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
#define RSTPPL_LOWER_COREBYPASS_SHIFT 12
#define RSTPPL_LOWER_GLBYPASS_SHIFT 11
#define RSTPPL_LOWER_PCISPEED_SHIFT 7
#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1
-#define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
+#define RSTPLL_LOWER_BOOTSTRAP_MASK \
+ (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
#define RSTPPL_LOWER_GLLOCK_SET (1 << 25)
#define RSTPPL_LOWER_CORELOCK_SET (1 << 24)
@@ -456,9 +464,9 @@
#define GLPCI_ARB_LOWER_VO2_SET (1 << 22)
#define GLPCI_ARB_LOWER_OV1_SET (1 << 21)
#define GLPCI_ARB_LOWER_OV0_SET (1 << 20)
-#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
-#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
-#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
+#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
+#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
+#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
#define GLPCI_ARB_LOWER_CPRE_SET (1<<11)
#define GLPCI_ARB_LOWER_PRE2_SET (1<<10)
#define GLPCI_ARB_LOWER_PRE1_SET (1<<9)
@@ -489,13 +497,13 @@
#define GLPCI_ExtMSR (MSR_PCI + 0x201E)
#define GLPCI_SPARE (MSR_PCI + 0x201F)
-#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
-#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
-#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
-#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
-#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
-#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
-#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
+#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
+#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
+#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
+#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
+#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
+#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
+#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
@@ -522,15 +530,23 @@
#define MAX_COL_ADDR 17
/* GLIU typedefs */
-#define BM 1 /* Base Mask - map power of 2 size aligned region*/
+/* Base Mask - map power of 2 size aligned region*/
+#define BM 1
#define BMO 2 /* BM with an offset*/
#define R 3 /* Range - 4k range minimum*/
#define RO 4 /* R with offset*/
-#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
+/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
+#define SC 5
#define BMIO 6 /* Base Mask IO*/
#define SCIO 7 /* Swiss 0xCeese IO*/
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/
+/* Special marker for Shadow SC descriptors so setShadow proc is independent
+ * of CPU
+ */
+#define SC_SHADOW 8
+/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent
+ * of CPU
+ */
+#define R_SYSMEM 9
#define BMO_SMM 10 /* Special marker for SMM*/
#define BM_SMM 11 /* Special marker for SMM*/
#define BMO_DMM 12 /* Special marker for DMM*/
@@ -566,7 +582,7 @@
#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
-#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
+#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
@@ -612,12 +628,12 @@
#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
-#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
+#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
/* ------------------------ */
#define SMM_OFFSET 0x80400000 /* above 2GB */
-#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
+#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
/* DRAM_TERMINATED affects how the DELAY register is set. */
#define DRAM_TERMINATED 'T'
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index 4a217b2..6ad9109 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -73,13 +73,15 @@ static inline int is_e0_later_in_bsp(int nodeid)
if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
return 1;
- if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0
+ if (nodeid == 0)
+ // we don't need to do that for node 0 in core0/node0
return !is_cpu_pre_e0();
- }
- // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
+
+ // d0 will be treated as e0 with this methods, but the d0
+ // nb_cfg_54 always 0
pci_devfn_t dev;
- dev = PCI_DEV(0, 0x18+nodeid,2);
+ dev = PCI_DEV(0, 0x18+nodeid, 2);
val_old = pci_read_config32(dev, 0x80);
val = val_old;
val |= (1<<3);
@@ -87,9 +89,11 @@ static inline int is_e0_later_in_bsp(int nodeid)
val = pci_read_config32(dev, 0x80);
e0_later = !!(val & (1<<3));
- if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
- pci_write_config32(dev, 0x80, val_old); // restore it
- }
+ if (e0_later)
+ // pre_e0 bit 3 always be 0 and can not be changed
+ // restore it
+ pci_write_config32(dev, 0x80, val_old);
+
return e0_later;
}
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 31af3e6..614c576 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -2,7 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 7da6cd1..b65c23b 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -42,7 +42,7 @@
void amd_setup_mtrrs(void);
-static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned index)
+static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
{
msr_t result;
__asm__ __volatile__ (
@@ -53,7 +53,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned index)
return result;
}
-static inline __attribute__((always_inline)) void wrmsr_amd(unsigned index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index,
+ msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h
index fc1e863..77df7b0 100644
--- a/src/include/cpu/amd/powernow.h
+++ b/src/include/cpu/amd/powernow.h
@@ -2,7 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Rudolf Marek <r.marek at assembler.cz>
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +19,6 @@
#define POWERNOW_H
void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP);
-void amd_powernow_update_fadt(acpi_fadt_t * fadt);
+void amd_powernow_update_fadt(acpi_fadt_t *fadt);
#endif
diff --git a/src/include/cpu/amd/sc520.h b/src/include/cpu/amd/sc520.h
index c79e99e..4e748be 100644
--- a/src/include/cpu/amd/sc520.h
+++ b/src/include/cpu/amd/sc520.h
@@ -10,11 +10,11 @@ struct parreg {
unsigned long reg[16];
};
-#define PARREG (struct parreg *)0xfffef088
+#define PARREG ((struct parreg *)0xfffef088)
//static volatile struct parreg *par = PARREG;
-#define MMCRPIC (struct mmcrpic *) 0xfffefd00
+#define MMCRPIC ((struct mmcrpic *) 0xfffefd00)
//static volatile struct mmcrpic *pic = MMCRPIC;
#define M_GINT_MODE 1
@@ -151,7 +151,7 @@ struct gptimers {
struct watchdog {
unsigned short ctl;
unsigned short cntll;
- unsigned short cntlh;
+ unsigned short cntlh;
unsigned char pad[10];
};
@@ -308,4 +308,4 @@ struct mmcr {
};
-#define MMCRDEFAULT (struct mmcr *) 0xfffef000
+#define MMCRDEFAULT ((struct mmcr *) 0xfffef000)
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index dd89a8c..a78dd2f 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -7,10 +7,10 @@
void cpu_initialize(unsigned int cpu_index);
struct bus;
void initialize_cpus(struct bus *cpu_bus);
-void asmlinkage secondary_cpu_init(unsigned int cpu_index);
+asmlinkage void secondary_cpu_init(unsigned int cpu_index);
int cpu_phys_address_size(void);
-#define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
+#define __cpu_driver __attribute__ ((used, __section__(".rodata.cpu_driver")))
#ifndef __SIMPLE_DEVICE__
/** start of compile time generated pci driver array */
extern struct cpu_driver _cpu_drivers[];
diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h
index 587e433..1af04e7 100644
--- a/src/include/cpu/intel/l2_cache.h
+++ b/src/include/cpu/intel/l2_cache.h
@@ -57,7 +57,7 @@
#define BBLCR3_L2_SIZE_2M (0x08 << 13)
#define BBLCR3_L2_SIZE_4M (0x10 << 13)
/* bits [22:20] */
-#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20);
+#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20)
/* TODO: This bitmask does not agree with Intel's documentation.
* Get confirmation one way or another.
*/
@@ -83,10 +83,12 @@
#define L2CMD_MESI_I 0
extern int calculate_l2_latency(void);
-extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command);
+extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way,
+ u8 command);
extern int read_l2(u32 address);
extern int write_l2(u32 address, u32 data);
-extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low);
+extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high,
+ u32 data_low);
extern int calculate_l2_cache_size(void);
extern int calculate_l2_physical_address_range(void);
extern int set_l2_ecc(void);
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 1f967ce..3a9e989 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -24,9 +24,9 @@ void *setup_stack_and_mtrrs(void);
/* romstage_main is called from the cache-as-ram assembly file to prepare
* CAR stack guards.*/
-void * asmlinkage romstage_main(unsigned long bist);
+asmlinkage void *romstage_main(unsigned long bist);
/* romstage_after_car() is the C function called after cache-as-ram has
* been torn down. It is responsible for loading the ramstage. */
-void asmlinkage romstage_after_car(void);
+asmlinkage void romstage_after_car(void);
#endif /* _CPU_INTEL_ROMSTAGE_H */
diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h
index 175b1e8..dafa791 100644
--- a/src/include/cpu/x86/cr.h
+++ b/src/include/cpu/x86/cr.h
@@ -42,7 +42,7 @@ static alwaysinline CRx_TYPE read_cr0(void)
CRx_TYPE value;
__asm__ __volatile__ (
"mov %%cr0, %0"
- : CRx_RET (value)
+ : CRx_RET(value)
:
: COMPILER_BARRIER
);
@@ -54,7 +54,7 @@ static alwaysinline void write_cr0(CRx_TYPE data)
__asm__ __volatile__ (
"mov %0, %%cr0"
:
- : CRx_IN (data)
+ : CRx_IN(data)
: COMPILER_BARRIER
);
}
@@ -64,7 +64,7 @@ static alwaysinline CRx_TYPE read_cr4(void)
CRx_TYPE value;
__asm__ __volatile__ (
"mov %%cr4, %0"
- : CRx_RET (value)
+ : CRx_RET(value)
:
: COMPILER_BARRIER
);
@@ -76,7 +76,7 @@ static alwaysinline void write_cr4(CRx_TYPE data)
__asm__ __volatile__ (
"mov %0, %%cr4"
:
- : CRx_IN (data)
+ : CRx_IN(data)
: COMPILER_BARRIER
);
}
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index dfcb4da..6f3cbdb 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -13,19 +13,21 @@
# define NEED_LAPIC 0
#endif
-static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
+static inline __attribute__((always_inline)) unsigned long lapic_read(
+ unsigned long reg)
{
return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
}
-static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
+static inline __attribute__((always_inline)) void lapic_write(unsigned long reg,
+ unsigned long v)
{
*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
}
static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
{
- do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
+ do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
}
static inline void enable_lapic(void)
@@ -67,7 +69,8 @@ void stop_this_cpu(void);
#if !defined(__PRE_RAM__)
-#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr))))
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((struct __xchg_dummy *)(x))
@@ -77,27 +80,28 @@ struct __xchg_dummy { unsigned long a[100]; };
* Note 2: xchg has side effect, so that attribute volatile is necessary,
* but generally the primitive is invalid, *ptr is output argument. --ANK
*/
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+ int size)
{
switch (size) {
- case 1:
- __asm__ __volatile__("xchgb %b0,%1"
- :"=q" (x)
- :"m" (*__xg(ptr)), "0" (x)
- :"memory");
- break;
- case 2:
- __asm__ __volatile__("xchgw %w0,%1"
- :"=r" (x)
- :"m" (*__xg(ptr)), "0" (x)
- :"memory");
- break;
- case 4:
- __asm__ __volatile__("xchgl %0,%1"
- :"=r" (x)
- :"m" (*__xg(ptr)), "0" (x)
- :"memory");
- break;
+ case 1:
+ __asm__ __volatile__("xchgb %b0,%1"
+ : "=q" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__("xchgw %w0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__("xchgl %0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
}
return x;
}
@@ -111,11 +115,11 @@ static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
#ifdef X86_GOOD_APIC
# define FORCE_READ_AROUND_WRITE 0
# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x,y) lapic_write((x),(y))
+# define lapic_write_around(x, y) lapic_write((x), (y))
#else
# define FORCE_READ_AROUND_WRITE 1
# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x,y) lapic_write_atomic((x),(y))
+# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
#endif
static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index b9b4d57..4a85556 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -26,7 +26,7 @@ struct bus;
static inline void mfence(void)
{
- __asm__ __volatile__("mfence\t\n": : :"memory");
+ __asm__ __volatile__("mfence\t\n" : : : "memory");
}
/* The sequence of the callbacks are in calling order. */
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index f830f3b..8070000 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -17,29 +17,28 @@ static void wrmsr(unsigned long index, msr_t msr)
#else
-typedef struct msr_struct
-{
- unsigned lo;
- unsigned hi;
+typedef struct msr_struct {
+ unsigned int lo;
+ unsigned int hi;
} msr_t;
-typedef struct msrinit_struct
-{
- unsigned index;
+typedef struct msrinit_struct {
+ unsigned int index;
msr_t msr;
} msrinit_t;
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
-msr_t soc_msr_read(unsigned index);
-void soc_msr_write(unsigned index, msr_t msr);
+msr_t soc_msr_read(unsigned int index);
+void soc_msr_write(unsigned int index, msr_t msr);
/* Handle MSR references in the other source code */
-static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
+static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
{
return soc_msr_read(index);
}
-static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
+ msr_t msr)
{
soc_msr_write(index, msr);
}
@@ -55,7 +54,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms
* these functions to always be inlined by adding the qualifier
* __attribute__((always_inline)) to their declaration.
*/
-static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
+static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
{
msr_t result;
__asm__ __volatile__ (
@@ -66,7 +65,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
return result;
}
-static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
+ msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index d9f38f5..b070d44 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -25,12 +25,12 @@
#define SMRR_PHYS_BASE 0x1f2
#define SMRR_PHYS_MASK 0x1f3
-#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
-#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
+#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
+#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
#define MTRR_PHYS_MASK_VALID (1 << 11)
-#define NUM_FIXED_RANGES 88
-#define RANGES_PER_FIXED_MTRR 8
+#define NUM_FIXED_RANGES 88
+#define RANGES_PER_FIXED_MTRR 8
#define MTRR_FIX_64K_00000 0x250
#define MTRR_FIX_16K_80000 0x258
#define MTRR_FIX_16K_A0000 0x259
@@ -43,7 +43,7 @@
#define MTRR_FIX_4K_F0000 0x26e
#define MTRR_FIX_4K_F8000 0x26f
-#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
+#if !defined(__ASSEMBLER__) && !defined(__PRE_RAM__)
#include <stdint.h>
#include <stddef.h>
@@ -87,7 +87,8 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
#endif
#if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__)
-void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
+void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+ unsigned int type);
int get_free_var_mtrr(void);
#endif
@@ -99,9 +100,9 @@ static inline unsigned int fms(unsigned int x)
int r;
__asm__("bsrl %1,%0\n\t"
- "jnz 1f\n\t"
- "movl $0,%0\n"
- "1:" : "=r" (r) : "g" (x));
+ "jnz 1f\n\t"
+ "movl $0,%0\n"
+ "1:" : "=r" (r) : "g" (x));
return r;
}
@@ -111,9 +112,9 @@ static inline unsigned int fls(unsigned int x)
int r;
__asm__("bsfl %1,%0\n\t"
- "jnz 1f\n\t"
- "movl $32,%0\n"
- "1:" : "=r" (r) : "g" (x));
+ "jnz 1f\n\t"
+ "movl $32,%0\n"
+ "1:" : "=r" (r) : "g" (x));
return r;
}
#endif
@@ -131,7 +132,7 @@ static inline unsigned int fls(unsigned int x)
*/
#define CACHE_TMP_RAMTOP (16<<20)
-#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
@@ -146,7 +147,8 @@ static inline unsigned int fls(unsigned int x)
# define CACHE_ROM_SIZE CONFIG_ROM_SIZE
# else
# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
-# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
+# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \
+# (2 * CONFIG_ROM_SIZE))
# error "CACHE_ROM_SIZE is not optimal."
# endif
# endif
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 0489ece..1892119 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -474,8 +474,10 @@ void northbridge_smi_handler(void);
void southbridge_smi_handler(void);
#else
void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
-void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
+void northbridge_smi_handler(unsigned int node,
+ smm_state_save_area_t *state_save);
+void southbridge_smi_handler(unsigned int node,
+ smm_state_save_area_t *state_save);
#endif /* CONFIG_SMM_TSEG */
void mainboard_smi_gpi(u32 gpi_sts);
int mainboard_smi_apmc(u8 data);
@@ -511,13 +513,13 @@ struct smm_module_params {
};
/* smm_handler_t is called with arg of smm_module_params pointer. */
-typedef void asmlinkage (*smm_handler_t)(void *);
+typedef asmlinkage void (*smm_handler_t)(void *);
#ifdef __SMM__
/* SMM Runtime helpers. */
/* Entry point for SMM modules. */
-void asmlinkage smm_handler_start(void *params);
+asmlinkage void smm_handler_start(void *params);
/* Retrieve SMM save state for a given CPU. WARNING: This does not take into
* account CPUs which are configured to not save their state to RAM. */
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index e4ca0e7..5a7fbc2 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -12,8 +12,8 @@
#endif
struct tsc_struct {
- unsigned lo;
- unsigned hi;
+ unsigned int lo;
+ unsigned int hi;
};
typedef struct tsc_struct tsc_t;
diff --git a/src/include/delay.h b/src/include/delay.h
index b3d8ed9..8f894d2 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -3,7 +3,7 @@
void init_timer(void);
-void udelay(unsigned usecs);
-void mdelay(unsigned msecs);
-void delay(unsigned secs);
+void udelay(unsigned int usecs);
+void mdelay(unsigned int msecs);
+void delay(unsigned int secs);
#endif /* DELAY_H */
diff --git a/src/include/device/azalia.h b/src/include/device/azalia.h
index 2af4696..7abf8e8 100644
--- a/src/include/device/azalia.h
+++ b/src/include/device/azalia.h
@@ -25,10 +25,10 @@
*/
enum AzaliaPinCfgPortConnectivity {
- AZALIA_PINCFG_PORT_JACK = 0b00,
- AZALIA_PINCFG_PORT_NC = 0b01,
- AZALIA_PINCFG_PORT_FIXED = 0b10,
- AZALIA_PINCFG_PORT_MULTIPLE = 0b11,
+ AZALIA_PINCFG_PORT_JACK = 0,
+ AZALIA_PINCFG_PORT_NC = 1,
+ AZALIA_PINCFG_PORT_FIXED = 2,
+ AZALIA_PINCFG_PORT_MULTIPLE = 3,
};
enum AzaliaPinCfgLocationGross {
@@ -113,7 +113,7 @@ enum AzaliaPinCfgMisc {
union AzaliaPinConfiguration {
unsigned int value;
- struct __attribute__((aligned(4),packed)) {
+ struct __attribute__((aligned(4), packed)) {
enum AzaliaPinCfgPortConnectivity port:2;
unsigned char location:6;
enum AzaliaPinCfgDefaultDevice device:4;
diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h
index e1cbafe..e47d228 100644
--- a/src/include/device/azalia_device.h
+++ b/src/include/device/azalia_device.h
@@ -33,19 +33,24 @@ extern const u32 cim_verb_data_size;
extern const u32 pc_beep_verbs[];
extern const u32 pc_beep_verbs_size;
-#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); \
+#define AZALIA_ARRAY_SIZES \
+ const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); \
const u32 cim_verb_data_size = sizeof(cim_verb_data)
-#define AZALIA_PIN_CFG(codec, pin, val) \
- ((codec) << 28) | ((pin) << 20) | ( 0x71c << 8) | ((val) & 0xff), \
- ((codec) << 28) | ((pin) << 20) | ( 0x71d << 8) | (((val) >> 8) & 0xff), \
- ((codec) << 28) | ((pin) << 20) | ( 0x71e << 8) | (((val) >> 16) & 0xff), \
- ((codec) << 28) | ((pin) << 20) | ( 0x71f << 8) | (((val) >> 24) & 0xff)
-
-#define AZALIA_SUBVENDOR(codec, val) \
- ((codec) << 28) | (0x01720 << 8) | ((val) & 0xff), \
- ((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff), \
- ((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff), \
- ((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff)
+#define AZALIA_PIN_CFG(codec, pin, val) \
+ (((codec) << 28) | ((pin) << 20) | (0x71c << 8) \
+ | ((val) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | (0x71d << 8) \
+ | (((val) >> 8) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | (0x71e << 8) \
+ | (((val) >> 16) & 0xff)), \
+ (((codec) << 28) | ((pin) << 20) | (0x71f << 8) \
+ | (((val) >> 24) & 0xff))
+
+#define AZALIA_SUBVENDOR(codec, val) \
+ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \
+ (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
+ (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
+ (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))
#endif /* DEVICE_AZALIA_H */
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 284c039..a318629 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -17,7 +17,7 @@
struct device;
#ifndef __SIMPLE_DEVICE__
-typedef struct device * device_t;
+typedef struct device *device_t;
struct pci_operations;
struct pci_bus_operations;
struct i2c_bus_operations;
@@ -54,11 +54,13 @@ struct device_operations {
void (*set_link)(device_t dev, unsigned int link);
void (*reset_bus)(struct bus *bus);
#if CONFIG_GENERATE_SMBIOS_TABLES
- int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+ int (*get_smbios_data)(device_t dev, int *handle,
+ unsigned long *current);
void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t);
#endif
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, struct acpi_rsdp *rsdp);
+ unsigned long (*write_acpi_tables)(device_t dev, unsigned long start,
+ struct acpi_rsdp *rsdp);
void (*acpi_fill_ssdt_generator)(device_t dev);
void (*acpi_inject_dsdt_generator)(device_t dev);
const char *(*acpi_name)(device_t dev);
@@ -82,20 +84,20 @@ static inline void device_noop(struct device *dev) {}
struct bus {
- ROMSTAGE_CONST struct device * dev; /* This bridge device */
- ROMSTAGE_CONST struct device * children; /* devices behind this bridge */
- ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */
- unsigned bridge_ctrl; /* Bridge control register */
+ ROMSTAGE_CONST struct device *dev; /* This bridge device */
+ ROMSTAGE_CONST struct device *children; /* devices behind this bridge */
+ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */
+ unsigned int bridge_ctrl; /* Bridge control register */
uint16_t bridge_cmd; /* Bridge command register */
unsigned char link_num; /* The index of this link */
- uint16_t secondary; /* secondary bus number */
+ uint16_t secondary; /* secondary bus number */
uint16_t subordinate; /* max subordinate bus number */
unsigned char cap; /* PCi capability offset */
- uint32_t hcdn_reg; /* For HyperTransport link */
+ uint32_t hcdn_reg; /* For HyperTransport link */
- unsigned reset_needed : 1;
- unsigned disable_relaxed_ordering : 1;
- unsigned ht_link_up : 1;
+ unsigned int reset_needed : 1;
+ unsigned int disable_relaxed_ordering : 1;
+ unsigned int ht_link_up : 1;
};
/*
@@ -111,22 +113,24 @@ struct pci_irq_info {
};
struct device {
- ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge
+ ROMSTAGE_CONST struct bus *bus; /* bus this device is on, for bridge
* devices, it is the up stream bus */
- ROMSTAGE_CONST struct device * sibling; /* next device on this bus */
+ ROMSTAGE_CONST struct device *sibling; /* next device on this bus */
- ROMSTAGE_CONST struct device * next; /* chain of all devices */
+ ROMSTAGE_CONST struct device *next; /* chain of all devices */
struct device_path path;
- unsigned vendor;
- unsigned device;
+ unsigned int vendor;
+ unsigned int device;
u16 subsystem_vendor;
u16 subsystem_device;
unsigned int class; /* 3 bytes: (base, sub, prog-if) */
unsigned int hdr_type; /* PCI header type */
unsigned int enabled : 1; /* set if we should enable the device */
- unsigned int initialized : 1; /* set if we have initialized the device */
+ unsigned int initialized : 1; /* set if we have initialized the
+ * device
+ */
unsigned int on_mainboard : 1;
struct pci_irq_info pci_irq_info[4];
u8 command;
@@ -195,17 +199,18 @@ void run_bios(struct device *dev, unsigned long addr);
/* Helper functions */
device_t find_dev_path(struct bus *parent, struct device_path *path);
device_t alloc_find_dev(struct bus *parent, struct device_path *path);
-device_t dev_find_device (u16 vendor, u16 device, device_t from);
-device_t dev_find_class (unsigned int class, device_t from);
+device_t dev_find_device(u16 vendor, u16 device, device_t from);
+device_t dev_find_class(unsigned int class, device_t from);
device_t dev_find_path(device_t prev_match, enum device_path_type path_type);
-device_t dev_find_slot (unsigned int bus, unsigned int devfn);
-device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
+device_t dev_find_slot(unsigned int bus, unsigned int devfn);
+device_t dev_find_slot_on_smbus(unsigned int bus, unsigned int addr);
device_t dev_find_slot_pnp(u16 port, u16 device);
-device_t dev_find_lapic(unsigned apic_id);
+device_t dev_find_lapic(unsigned int apic_id);
int dev_count_cpu(void);
-device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled);
-void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread);
+device_t add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled);
+void set_cpu_topology(device_t cpu, unsigned int node, unsigned int package,
+ unsigned int core, unsigned int thread);
#define amd_cpu_topology(cpu, node, core) \
set_cpu_topology(cpu, node, 0, core, 0)
@@ -214,7 +219,7 @@ void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned co
set_cpu_topology(cpu, 0, package, core, thread)
/* Debug functions */
-void print_resource_tree(struct device * root, int debug_level,
+void print_resource_tree(struct device *root, int debug_level,
const char *msg);
void show_devs_tree(struct device *dev, int debug_level, int depth);
void show_devs_subtree(struct device *root, int debug_level, const char *msg);
@@ -222,7 +227,7 @@ void show_all_devs(int debug_level, const char *msg);
void show_all_devs_tree(int debug_level, const char *msg);
void show_one_resource(int debug_level, struct device *dev,
struct resource *resource, const char *comment);
-void show_all_devs_resources(int debug_level, const char* msg);
+void show_all_devs_resources(int debug_level, const char *msg);
/* Rounding for boundaries.
* Due to some chip bugs, go ahead and round IO to 16
@@ -252,7 +257,8 @@ void scan_lpc_bus(device_t bus);
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
#define reserved_ram_resource(dev, idx, basek, sizek) \
- fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE)
+ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \
+ | IORESOURCE_RESERVE)
#define bad_ram_resource(dev, idx, basek, sizek) \
reserved_ram_resource((dev), (idx), (basek), (sizek))
@@ -268,13 +274,13 @@ u32 find_pci_tolm(struct bus *bus);
#else /* vv __SIMPLE_DEVICE__ vv */
-ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus,
+ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus,
unsigned int devfn);
ROMSTAGE_CONST struct device *dev_find_next_pci_device(
- ROMSTAGE_CONST struct device *previous_dev);
-ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus,
+ ROMSTAGE_CONST struct device *previous_dev);
+ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
unsigned int addr);
-ROMSTAGE_CONST struct device * dev_find_slot_pnp(u16 port, u16 device);
+ROMSTAGE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device);
#endif
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 905aa84..e577c21 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -106,35 +106,35 @@ typedef union dimm_flags_st {
struct {
/* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See:
* Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */
- unsigned pins_mirrored:1;
+ unsigned int pins_mirrored:1;
/* Module can work at 1.50V - All DIMMS must be 1.5V operable */
- unsigned operable_1_50V:1;
+ unsigned int operable_1_50V:1;
/* Module can work at 1.35V */
- unsigned operable_1_35V:1;
+ unsigned int operable_1_35V:1;
/* Module can work at 1.20V */
- unsigned operable_1_25V:1;
+ unsigned int operable_1_25V:1;
/* Has an 8-bit bus extension, meaning the DIMM supports ECC */
- unsigned is_ecc:1;
+ unsigned int is_ecc:1;
/* DLL-Off Mode Support */
- unsigned dll_off_mode:1;
+ unsigned int dll_off_mode:1;
/* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */
- unsigned rzq6_supported:1;
+ unsigned int rzq6_supported:1;
/* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */
- unsigned rzq7_supported:1;
+ unsigned int rzq7_supported:1;
/* Partial Array Self Refresh */
- unsigned pasr:1;
+ unsigned int pasr:1;
/* On-die Thermal Sensor Readout */
- unsigned odts:1;
+ unsigned int odts:1;
/* Auto Self Refresh */
- unsigned asr:1;
+ unsigned int asr:1;
/* Extended temperature range supported */
- unsigned ext_temp_range:1;
+ unsigned int ext_temp_range:1;
/* Operating at extended temperature requires 2X refresh rate */
- unsigned ext_temp_refresh:1;
+ unsigned int ext_temp_refresh:1;
/* Thermal sensor incorporated */
- unsigned therm_sensor:1;
+ unsigned int therm_sensor:1;
};
- unsigned raw;
+ unsigned int raw;
} dimm_flags_t;
/**
@@ -200,12 +200,12 @@ typedef u8 spd_raw_data[256];
u16 spd_ddr3_calc_crc(u8 *spd, int len);
u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
-int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data);
+int spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd_data);
int dimm_is_registered(enum spd_dimm_type type);
-void dram_print_spd_ddr3(const dimm_attr * dimm);
-int spd_xmp_decode_ddr3(dimm_attr * dimm,
- spd_raw_data spd,
- enum ddr3_xmp_profile profile);
+void dram_print_spd_ddr3(const dimm_attr *dimm);
+int spd_xmp_decode_ddr3(dimm_attr *dimm,
+ spd_raw_data spd,
+ enum ddr3_xmp_profile profile);
/**
* \brief Read double word from specified address
diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h
index 8af94d9..4b340e8 100644
--- a/src/include/device/hypertransport_def.h
+++ b/src/include/device/hypertransport_def.h
@@ -21,8 +21,10 @@
static inline bool offset_unit_id(bool is_sb_ht_chain)
{
- bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
- return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || is_sb_ht_chain);
+ bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
+ || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
+ return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ || is_sb_ht_chain);
}
#endif /* DEVICE_HYPERTRANSPORT_DEF_H */
diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h
index d8a793c..6115bd1 100644
--- a/src/include/device/i2c.h
+++ b/src/include/device/i2c.h
@@ -32,35 +32,36 @@ enum i2c_address_mode {
I2C_MODE_10_BIT
};
-struct i2c_seg
-{
+struct i2c_seg {
int read;
uint8_t chip;
uint8_t *buf;
int len;
};
-int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count);
+int platform_i2c_transfer(unsigned int bus, struct i2c_seg *segments,
+ int count);
#define SOFTWARE_I2C_MAX_BUS 10 /* increase as necessary */
struct software_i2c_ops {
- void (*set_sda)(unsigned bus, int high);
- void (*set_scl)(unsigned bus, int high);
- int (*get_sda)(unsigned bus);
- int (*get_scl)(unsigned bus);
+ void (*set_sda)(unsigned int bus, int high);
+ void (*set_scl)(unsigned int bus, int high);
+ int (*get_sda)(unsigned int bus);
+ int (*get_scl)(unsigned int bus);
};
extern struct software_i2c_ops *software_i2c[];
-int software_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count);
-void software_i2c_wedge_ack(unsigned bus, u8 chip);
-void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bit_count);
-void software_i2c_wedge_write(unsigned bus, u8 chip, u8 reg, int bit_count);
+int software_i2c_transfer(unsigned int bus, struct i2c_seg *segments,
+ int count);
+void software_i2c_wedge_ack(unsigned int bus, u8 chip);
+void software_i2c_wedge_read(unsigned int bus, u8 chip, u8 reg, int bit_count);
+void software_i2c_wedge_write(unsigned int bus, u8 chip, u8 reg, int bit_count);
-int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data,
+int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data,
uint8_t mask, uint8_t shift);
-int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data,
+int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t data,
uint8_t mask, uint8_t shift);
/*
@@ -69,7 +70,7 @@ int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data,
* Need this ugly stub to arbitrate since I2C device drivers hardcode
* 'i2c_transfer()' as their entry point.
*/
-static inline int i2c_transfer(unsigned bus, struct i2c_seg *segments,
+static inline int i2c_transfer(unsigned int bus, struct i2c_seg *segments,
int count)
{
if (CONFIG_SOFTWARE_I2C)
@@ -84,11 +85,13 @@ static inline int i2c_transfer(unsigned bus, struct i2c_seg *segments,
*
* [start][slave addr][r][data][stop]
*/
-static inline int i2c_read_raw(unsigned bus, uint8_t chip, uint8_t *data,
+static inline int i2c_read_raw(unsigned int bus, uint8_t chip, uint8_t *data,
int len)
{
- struct i2c_seg seg =
- { .read = 1, .chip = chip, .buf = data, .len = len };
+ struct i2c_seg seg = {
+ .read = 1, .chip = chip, .buf = data, .len = len
+ };
+
return i2c_transfer(bus, &seg, 1);
}
@@ -97,11 +100,13 @@ static inline int i2c_read_raw(unsigned bus, uint8_t chip, uint8_t *data,
*
* [start][slave addr][w][data][stop]
*/
-static inline int i2c_write_raw(unsigned bus, uint8_t chip, uint8_t *data,
- int len)
+static inline int i2c_write_raw(unsigned int bus, uint8_t chip, uint8_t *data,
+ int len)
{
- struct i2c_seg seg =
- { .read = 0, .chip = chip, .buf = data, .len = len };
+ struct i2c_seg seg = {
+ .read = 0, .chip = chip, .buf = data, .len = len
+ };
+
return i2c_transfer(bus, &seg, 1);
}
@@ -110,7 +115,7 @@ static inline int i2c_write_raw(unsigned bus, uint8_t chip, uint8_t *data,
*
* [start][slave addr][w][register addr][start][slave addr][r][data...][stop]
*/
-static inline int i2c_read_bytes(unsigned bus, uint8_t chip, uint8_t reg,
+static inline int i2c_read_bytes(unsigned int bus, uint8_t chip, uint8_t reg,
uint8_t *data, int len)
{
struct i2c_seg seg[2];
@@ -132,7 +137,7 @@ static inline int i2c_read_bytes(unsigned bus, uint8_t chip, uint8_t reg,
*
* [start][slave addr][w][register addr][start][slave addr][r][data][stop]
*/
-static inline int i2c_readb(unsigned bus, uint8_t chip, uint8_t reg,
+static inline int i2c_readb(unsigned int bus, uint8_t chip, uint8_t reg,
uint8_t *data)
{
struct i2c_seg seg[2];
@@ -154,7 +159,7 @@ static inline int i2c_readb(unsigned bus, uint8_t chip, uint8_t reg,
*
* [start][slave addr][w][register addr][data][stop]
*/
-static inline int i2c_writeb(unsigned bus, uint8_t chip, uint8_t reg,
+static inline int i2c_writeb(unsigned int bus, uint8_t chip, uint8_t reg,
uint8_t data)
{
struct i2c_seg seg;
diff --git a/src/include/device/path.h b/src/include/device/path.h
index 849b579..5109fda 100644
--- a/src/include/device/path.h
+++ b/src/include/device/path.h
@@ -38,66 +38,55 @@ enum device_path_type {
"DEVICE_PATH_SPI", \
}
-struct domain_path
-{
- unsigned domain;
+struct domain_path {
+ unsigned int domain;
};
-struct pci_path
-{
- unsigned devfn;
+struct pci_path {
+ unsigned int devfn;
};
-struct pnp_path
-{
- unsigned port;
- unsigned device;
+struct pnp_path {
+ unsigned int port;
+ unsigned int device;
};
-struct i2c_path
-{
- unsigned device;
- unsigned mode_10bit;
+struct i2c_path {
+ unsigned int device;
+ unsigned int mode_10bit;
};
-struct spi_path
-{
- unsigned cs;
+struct spi_path {
+ unsigned int cs;
};
-struct apic_path
-{
- unsigned apic_id;
- unsigned package_id;
- unsigned node_id;
- unsigned core_id;
- unsigned thread_id;
+struct apic_path {
+ unsigned int apic_id;
+ unsigned int package_id;
+ unsigned int node_id;
+ unsigned int core_id;
+ unsigned int thread_id;
};
-struct ioapic_path
-{
- unsigned ioapic_id;
+struct ioapic_path {
+ unsigned int ioapic_id;
};
-struct cpu_cluster_path
-{
- unsigned cluster;
+struct cpu_cluster_path {
+ unsigned int cluster;
};
-struct cpu_path
-{
- unsigned id;
+struct cpu_path {
+ unsigned int id;
};
-struct cpu_bus_path
-{
- unsigned id;
+struct cpu_bus_path {
+ unsigned int id;
};
-struct generic_path
-{
- unsigned id;
- unsigned subid;
+struct generic_path {
+ unsigned int id;
+ unsigned int subid;
};
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index e167752..3f3d36f 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -32,18 +32,22 @@
/* Common pci operations without a standard interface */
struct pci_operations {
/* set the Subsystem IDs for the PCI device */
- void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device);
+ void (*set_subsystem)(device_t dev, unsigned int vendor,
+ unsigned int device);
void (*set_L1_ss_latency)(device_t dev, unsigned int off);
};
/* Common pci bus operations */
struct pci_bus_operations {
- uint8_t (*read8) (struct bus *pbus, int bus, int devfn, int where);
- uint16_t (*read16) (struct bus *pbus, int bus, int devfn, int where);
- uint32_t (*read32) (struct bus *pbus, int bus, int devfn, int where);
- void (*write8) (struct bus *pbus, int bus, int devfn, int where, uint8_t val);
- void (*write16) (struct bus *pbus, int bus, int devfn, int where, uint16_t val);
- void (*write32) (struct bus *pbus, int bus, int devfn, int where, uint32_t val);
+ uint8_t (*read8)(struct bus *pbus, int bus, int devfn, int where);
+ uint16_t (*read16)(struct bus *pbus, int bus, int devfn, int where);
+ uint32_t (*read32)(struct bus *pbus, int bus, int devfn, int where);
+ void (*write8)(struct bus *pbus, int bus, int devfn, int where,
+ uint8_t val);
+ void (*write16)(struct bus *pbus, int bus, int devfn, int where,
+ uint16_t val);
+ void (*write32)(struct bus *pbus, int bus, int devfn, int where,
+ uint32_t val);
};
struct pci_driver {
@@ -53,7 +57,7 @@ struct pci_driver {
const unsigned short *devices;
};
-#define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
+#define __pci_driver __attribute__ ((used, __section__(".rodata.pci_driver")))
/** start of compile time generated pci driver array */
extern struct pci_driver _pci_drivers[];
/** end of compile time generated pci driver array */
@@ -69,26 +73,28 @@ void pci_dev_set_resources(device_t dev);
void pci_dev_enable_resources(device_t dev);
void pci_bus_enable_resources(device_t dev);
void pci_bus_reset(struct bus *bus);
-device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn);
+device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned int devfn);
void do_pci_scan_bridge(device_t bus,
void (*do_scan_bus)(struct bus *bus,
- unsigned min_devfn, unsigned max_devfn));
+ unsigned int min_devfn, unsigned int max_devfn));
void pci_scan_bridge(device_t bus);
-void pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn);
+void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
+ unsigned int max_devfn);
-uint8_t pci_moving_config8(struct device *dev, unsigned reg);
-uint16_t pci_moving_config16(struct device *dev, unsigned reg);
-uint32_t pci_moving_config32(struct device *dev, unsigned reg);
+uint8_t pci_moving_config8(struct device *dev, unsigned int reg);
+uint16_t pci_moving_config16(struct device *dev, unsigned int reg);
+uint32_t pci_moving_config32(struct device *dev, unsigned int reg);
struct resource *pci_get_resource(struct device *dev, unsigned long index);
-void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
+void pci_dev_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device);
void pci_dev_init(struct device *dev);
unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev);
-const char * pin_to_str(int pin);
+const char *pin_to_str(int pin);
int get_pci_irq_pins(device_t dev, device_t *parent_bdg);
-void pci_assign_irqs(unsigned bus, unsigned slot,
+void pci_assign_irqs(unsigned int bus, unsigned int slot,
const unsigned char pIntAtoD[4]);
const char *get_pci_class_name(device_t dev);
const char *get_pci_subclass_name(device_t dev);
@@ -100,20 +106,21 @@ static inline const struct pci_operations *ops_pci(device_t dev)
{
const struct pci_operations *pops;
pops = 0;
- if (dev && dev->ops) {
+ if (dev && dev->ops)
pops = dev->ops->ops_pci;
- }
return pops;
}
#endif /* ! __SIMPLE_DEVICE__ */
#ifdef __SIMPLE_DEVICE__
-unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last);
-unsigned pci_find_capability(pci_devfn_t dev, unsigned cap);
+unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap,
+ unsigned int last);
+unsigned int pci_find_capability(pci_devfn_t dev, unsigned int cap);
#else /* !__SIMPLE_DEVICE__ */
-unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last);
-unsigned pci_find_capability(device_t dev, unsigned cap);
+unsigned int pci_find_next_capability(device_t dev, unsigned int cap,
+ unsigned int last);
+unsigned int pci_find_capability(device_t dev, unsigned int cap);
#endif /* __SIMPLE_DEVICE__ */
void pci_early_bridge_init(void);
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
index e80cf2b..8a64870 100644
--- a/src/include/device/pci_ehci.h
+++ b/src/include/device/pci_ehci.h
@@ -21,9 +21,9 @@
#include <device/device.h>
#define EHCI_BAR_INDEX 0x10
-#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
+#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
-pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
+pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx);
u8 *pci_ehci_base_regs(pci_devfn_t dev);
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 7d59415..0232387 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -598,7 +598,7 @@
#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469
#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a
#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b
-#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462
+#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462
#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463
#define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450
@@ -2743,7 +2743,7 @@
#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030
#define PCI_VENDOR_ID_SIS 0x1039
-#define PCI_DEVICE_ID_SIS_AGP 0x0002
+#define PCI_DEVICE_ID_SIS_AGP 0x0002
/* SiS 761GX NORTH BRIDGE */
#define PCI_DEVICE_ID_SIS_SIS761 0x0761
diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h
index 3f09778..c1af82e 100644
--- a/src/include/device/pci_rom.h
+++ b/src/include/device/pci_rom.h
@@ -5,7 +5,7 @@
#include <arch/acpi.h>
#define PCI_ROM_HDR 0xAA55
-#define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' )
+#define PCI_DATA_HDR ((uint32_t)(('R' << 24) | ('I' << 16) | ('C' << 8) | 'P'))
#define PCI_RAM_IMAGE_START 0xD0000
#define PCI_VGA_RAM_IMAGE_START 0xC0000
@@ -35,7 +35,8 @@ struct pci_data {
};
struct rom_header *pci_rom_probe(struct device *dev);
-struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header);
+struct rom_header *pci_rom_load(struct device *dev,
+ struct rom_header *rom_header);
unsigned long
pci_rom_write_acpi_tables(struct device *device,
diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h
index cfed7c7..bb66317 100644
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@@ -31,7 +31,7 @@ extern struct device_operations pnp_ops;
/* PNP helper operations */
struct io_info {
- unsigned mask, set;
+ unsigned int mask, set;
};
struct pnp_info {
@@ -64,7 +64,7 @@ struct pnp_info {
#define PNP_MSCE 0x800000
struct io_info io0, io1, io2, io3;
};
-struct resource *pnp_get_resource(device_t dev, unsigned index);
+struct resource *pnp_get_resource(device_t dev, unsigned int index);
void pnp_enable_devices(struct device *dev, struct device_operations *ops,
unsigned int functions, struct pnp_info *info);
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index 768c86d..d794fb2 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -11,7 +11,8 @@
#define IORESOURCE_IRQ 0x00000400
#define IORESOURCE_DRQ 0x00000800
-#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_IRQ | IORESOURCE_DRQ)
+#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM \
+ | IORESOURCE_IRQ | IORESOURCE_DRQ)
#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
#define IORESOURCE_READONLY 0x00002000
@@ -19,14 +20,18 @@
#define IORESOURCE_RANGELENGTH 0x00008000
#define IORESOURCE_SHADOWABLE 0x00010000
#define IORESOURCE_BUS_HAS_VGA 0x00020000
-#define IORESOURCE_SUBTRACTIVE 0x00040000 /* This resource filters all of the unclaimed transactions
- * to the bus below.
- */
-#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
-#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */
-#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
-#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */
-#define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */
+/* This resource filters all of the unclaimed transactions to the bus below. */
+#define IORESOURCE_SUBTRACTIVE 0x00040000
+/* The IO resource has a bus below it. */
+#define IORESOURCE_BRIDGE 0x00080000
+/* The resource needs to be reserved in the coreboot table */
+#define IORESOURCE_RESERVE 0x10000000
+/* The IO resource assignment has been stored in the device */
+#define IORESOURCE_STORED 0x20000000
+/* An IO resource that has been assigned a value */
+#define IORESOURCE_ASSIGNED 0x40000000
+/* An IO resource the allocator must not change */
+#define IORESOURCE_FIXED 0x80000000
/* PCI specific resource bits (IORESOURCE_BITS) */
#define IORESOURCE_PCI64 (1<<0) /* 64bit long pci resource */
@@ -37,7 +42,7 @@ struct resource {
resource_t base; /* Base address of the resource */
resource_t size; /* Size of the resource */
resource_t limit; /* Largest valid value base + size -1 */
- ROMSTAGE_CONST struct resource* next; /* Next resource in the list */
+ ROMSTAGE_CONST struct resource *next; /* Next resource in the list */
unsigned long flags; /* Descriptions of the kind of resource */
unsigned long index; /* Bus specific per device resource id */
unsigned char align; /* Required alignment (log 2) of the resource */
@@ -46,25 +51,27 @@ struct resource {
};
/* Macros to generate index values for resources */
-#define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK)
+#define IOINDEX_SUBTRACTIVE(IDX, LINK) (0x10000000 + ((IDX) << 8) + LINK)
#define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff)
-#define IOINDEX(IDX,LINK) (((LINK) << 16) + IDX)
-#define IOINDEX_LINK(IDX) (( IDX & 0xf0000) >> 16)
+#define IOINDEX(IDX, LINK) (((LINK) << 16) + IDX)
+#define IOINDEX_LINK(IDX) ((IDX & 0xf0000) >> 16)
#define IOINDEX_IDX(IDX) (IDX & 0xffff)
/* Generic resource helper functions */
struct device;
struct bus;
-extern void compact_resources(struct device * dev);
-extern struct resource *probe_resource(struct device *dev, unsigned index);
-extern struct resource *new_resource(struct device * dev, unsigned index);
-extern struct resource *find_resource(struct device * dev, unsigned index);
+extern void compact_resources(struct device *dev);
+extern struct resource *probe_resource(struct device *dev, unsigned int index);
+extern struct resource *new_resource(struct device *dev, unsigned int index);
+extern struct resource *find_resource(struct device *dev, unsigned int index);
extern resource_t resource_end(struct resource *resource);
extern resource_t resource_max(struct resource *resource);
-extern void report_resource_stored(struct device * dev, struct resource *resource, const char *comment);
+extern void report_resource_stored(struct device *dev,
+ struct resource *resource, const char *comment);
-typedef void (*resource_search_t)(void *gp, struct device *dev, struct resource *res);
+typedef void (*resource_search_t)(void *gp, struct device *dev,
+ struct resource *res);
extern void search_bus_resources(struct bus *bus,
unsigned long type_mask, unsigned long type,
resource_search_t search, void *gp);
diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h
index ccbd694..d39eaf8 100644
--- a/src/include/device/smbus.h
+++ b/src/include/device/smbus.h
@@ -8,17 +8,17 @@
/* Common SMBus bus operations */
struct smbus_bus_operations {
- int (*quick_read) (device_t dev);
- int (*quick_write) (device_t dev);
- int (*recv_byte) (device_t dev);
- int (*send_byte) (device_t dev, u8 value);
- int (*read_byte) (device_t dev, u8 addr);
- int (*write_byte) (device_t dev, u8 addr, u8 value);
- int (*read_word) (device_t dev, u8 addr);
- int (*write_word) (device_t dev, u8 addr, u16 value);
+ int (*quick_read)(device_t dev);
+ int (*quick_write)(device_t dev);
+ int (*recv_byte)(device_t dev);
+ int (*send_byte)(device_t dev, u8 value);
+ int (*read_byte)(device_t dev, u8 addr);
+ int (*write_byte)(device_t dev, u8 addr, u8 value);
+ int (*read_word)(device_t dev, u8 addr);
+ int (*write_word)(device_t dev, u8 addr, u16 value);
int (*process_call)(device_t dev, u8 cmd, u16 data);
- int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer);
- int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
+ int (*block_read)(device_t dev, u8 cmd, u8 bytes, u8 *buffer);
+ int (*block_write)(device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
};
static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus)
@@ -35,17 +35,17 @@ static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus)
struct bus *get_pbus_smbus(device_t dev);
int smbus_set_link(device_t dev);
-int smbus_quick_read(device_t dev);
-int smbus_quick_write(device_t dev);
-int smbus_recv_byte(device_t dev);
-int smbus_send_byte(device_t dev, u8 byte);
-int smbus_read_byte(device_t dev, u8 addr);
-int smbus_write_byte(device_t dev, u8 addr, u8 val);
-int smbus_read_word(device_t dev, u8 addr);
-int smbus_write_word(device_t dev, u8 addr, u16 val);
+int smbus_quick_read(device_t dev);
+int smbus_quick_write(device_t dev);
+int smbus_recv_byte(device_t dev);
+int smbus_send_byte(device_t dev, u8 byte);
+int smbus_read_byte(device_t dev, u8 addr);
+int smbus_write_byte(device_t dev, u8 addr, u8 val);
+int smbus_read_word(device_t dev, u8 addr);
+int smbus_write_word(device_t dev, u8 addr, u16 val);
int smbus_process_call(device_t dev, u8 cmd, u16 data);
-int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer);
-int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
+int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer);
+int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS)
void smbus_switch_to_channel(uint8_t channel_number);
diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h
index f6ef560..f2632e7 100644
--- a/src/include/ip_checksum.h
+++ b/src/include/ip_checksum.h
@@ -1,5 +1,6 @@
#ifndef IP_CHECKSUM_H
#define IP_CHECKSUM_H
unsigned long compute_ip_checksum(const void *addr, unsigned long length);
-unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new);
+unsigned long add_ip_checksums(unsigned long offset, unsigned long sum,
+ unsigned long new);
#endif /* IP_CHECKSUM_H */
diff --git a/src/include/memrange.h b/src/include/memrange.h
index 759f8f5..75f9877 100644
--- a/src/include/memrange.h
+++ b/src/include/memrange.h
@@ -73,7 +73,7 @@ static inline unsigned long range_entry_tag(const struct range_entry *r)
}
static inline void range_entry_update_tag(struct range_entry *r,
- unsigned long new_tag)
+ unsigned long new_tag)
{
r->tag = new_tag;
}
@@ -89,14 +89,14 @@ static inline void range_entry_update_tag(struct range_entry *r,
/* Initialize memranges structure providing an optional array of range_entry
* to use as the free list. */
void memranges_init_empty(struct memranges *ranges, struct range_entry *free,
- size_t num_free);
+ size_t num_free);
/* Initialize and fill a memranges structure according to the
* mask and match type for all memory resources. Tag each entry with the
* specified type. */
void memranges_init(struct memranges *ranges,
- unsigned long mask, unsigned long match,
- unsigned long tag);
+ unsigned long mask, unsigned long match,
+ unsigned long tag);
/* Remove and free all entries within the memranges structure. */
void memranges_teardown(struct memranges *ranges);
@@ -107,8 +107,8 @@ void memranges_teardown(struct memranges *ranges);
* memranges_add_resources(range, IORESOURCE_CACHEABLE,
* IORESROUCE_CACHEABLE, my_cacheable_tag); */
void memranges_add_resources(struct memranges *ranges,
- unsigned long mask, unsigned long match,
- unsigned long tag);
+ unsigned long mask, unsigned long match,
+ unsigned long tag);
/* Add memory resources that match with the corresponding mask and match but
* also provide filter as additional check. The filter will return non-zero
@@ -119,31 +119,32 @@ void memranges_add_resources(struct memranges *ranges,
* IORESROUCE_CACHEABLE, my_cacheable_tag, filter); */
typedef int (*memrange_filter_t)(struct device *dev, struct resource *res);
void memranges_add_resources_filter(struct memranges *ranges,
- unsigned long mask, unsigned long match,
- unsigned long tag,
- memrange_filter_t filter);
+ unsigned long mask, unsigned long match,
+ unsigned long tag,
+ memrange_filter_t filter);
/* Fill all address ranges up to limit (exclusive) not covered by an entry by
* inserting new entries with the provided tag. */
void memranges_fill_holes_up_to(struct memranges *ranges,
- resource_t limit, unsigned long tag);
+ resource_t limit, unsigned long tag);
/* Create a hole in the range by deleting/modifying entries that overlap with
* the region specified by base and size. */
void memranges_create_hole(struct memranges *ranges,
- resource_t base, resource_t size);
+ resource_t base, resource_t size);
/* Insert a resource to the given memranges. All existing ranges
* covered by range specified by base and size will be removed before a
* new one is added. */
void memranges_insert(struct memranges *ranges,
- resource_t base, resource_t size, unsigned long tag);
+ resource_t base, resource_t size, unsigned long tag);
/* Update all entries with old_tag to new_tag. */
void memranges_update_tag(struct memranges *ranges, unsigned long old_tag,
- unsigned long new_tag);
+ unsigned long new_tag);
/* Returns next entry after the provided entry. NULL if r is last. */
struct range_entry *memranges_next_entry(struct memranges *ranges,
- const struct range_entry *r);
+ const struct range_entry *r);
+
#endif /* MEMRANGE_H_ */
diff --git a/src/include/nhlt.h b/src/include/nhlt.h
index 5b72320..f692b9a 100644
--- a/src/include/nhlt.h
+++ b/src/include/nhlt.h
@@ -320,7 +320,8 @@ struct nhlt_dmic_array_config {
/*
* Microphone array definitions may be found here:
- * https://msdn.microsoft.com/en-us/library/windows/hardware/dn613960%28v=vs.85%29.aspx
+ * https://msdn.microsoft.com/en-us/library/windows/hardware/
+ * dn613960%28v=vs.85%29.aspx
*/
enum {
NHLT_MIC_ARRAY_2CH_SMALL = 0xa,
diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h
index ea6637e..857c5c8 100644
--- a/src/include/pc80/i8259.h
+++ b/src/include/pc80/i8259.h
@@ -69,7 +69,7 @@
#define SLAVE_PIC_ICW3 0xa1
#define SLAVE_ID 0x02
-#define MASTER_PIC_OCW1 0x21
+#define MASTER_PIC_OCW1 0x21
#define SLAVE_PIC_OCW1 0xa1
#define IRQ2 (1 << 2)
#define ALL_IRQS 0xff
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 99fba9d..ef19a15 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -40,8 +40,10 @@
/* 2 values for divider stage reset, others for "testing purposes only" */
# define RTC_DIV_RESET1 0x60
# define RTC_DIV_RESET2 0x70
- /* Periodic intr. / Square wave rate select. 0 = none, 1 = 32.8kHz,... 15 = 2Hz */
-# define RTC_RATE_SELECT 0x0F
+ /* Periodic intr. / Square wave rate select. 0 = none,
+ * 1 = 32.8kHz,... 15 = 2Hz
+ */
+# define RTC_RATE_SELECT 0x0F
# define RTC_RATE_NONE 0x00
# define RTC_RATE_32786HZ 0x01
# define RTC_RATE_16384HZ 0x02
@@ -140,14 +142,12 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
* eg. the Century / AltCentury byte. So to be safe, disable
* RTC before changing any value.
*/
- if ((addr != RTC_CONTROL) && !(control_state & RTC_SET)) {
+ if ((addr != RTC_CONTROL) && !(control_state & RTC_SET))
cmos_write_inner(control_state | RTC_SET, RTC_CONTROL);
- }
cmos_write_inner(val, addr);
/* reset to prior configuration */
- if ((addr != RTC_CONTROL) && !(control_state & RTC_SET)) {
+ if ((addr != RTC_CONTROL) && !(control_state & RTC_SET))
cmos_write_inner(control_state, RTC_CONTROL);
- }
}
static inline void cmos_disable_rtc(void)
@@ -184,12 +184,14 @@ void cmos_check_update_date(void);
enum cb_err set_option(const char *name, void *val);
enum cb_err get_option(void *dest, const char *name);
-unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
+unsigned int read_option_lowlevel(unsigned int start, unsigned int size,
+ unsigned int def);
#else /* defined(__ROMCC__) */
#include <drivers/pc80/rtc/mc146818rtc_early.c>
#endif /* !defined(__ROMCC__) */
-#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
+#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \
+ CMOS_VLEN_ ##name, (default))
#if CONFIG_CMOS_POST
#if CONFIG_USE_OPTION_TABLE
diff --git a/src/include/reg_script.h b/src/include/reg_script.h
index d7ed326..74f55d1 100644
--- a/src/include/reg_script.h
+++ b/src/include/reg_script.h
@@ -107,11 +107,12 @@ struct reg_script_bus_entry {
void (*reg_script_write)(struct reg_script_context *ctx);
};
-#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used,section (".rsbe_init")))
+#define REG_SCRIPT_TABLE_ATTRIBUTE \
+ __attribute__ ((used, section(".rsbe_init")))
-#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \
- const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \
- REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_;
+#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \
+ const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \
+ REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_
/* Internal helper Macros. */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index c5de9c3..15d8a10 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -45,7 +45,7 @@ int rmodule_load_alignment(const struct rmodule *m);
* load_offset is the address to load and relocate the rmodule.
* region_alignment must be a power of 2. */
int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size,
- size_t *region_size, int *load_offset);
+ size_t *region_size, int *load_offset);
/* Support for loading rmodule stages. This API is only available when
* using dynamic cbmem because it uses the dynamic cbmem API to obtain
@@ -72,7 +72,7 @@ struct rmodule {
#if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
/* Rmodules have an entry point of named _start. */
#define RMODULE_ENTRY(entry_) \
- void _start(void *) __attribute__((alias (STRINGIFY(entry_))))
+ void _start(void *) __attribute__((alias(STRINGIFY(entry_))))
#else
#define RMODULE_ENTRY(entry_)
#endif
diff --git a/src/include/rtc.h b/src/include/rtc.h
index e654785..f006e7a 100644
--- a/src/include/rtc.h
+++ b/src/include/rtc.h
@@ -16,8 +16,7 @@
#ifndef _RTC_H_
#define _RTC_H_
-struct rtc_time
-{
+struct rtc_time {
int sec;
int min;
int hour;
diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h
index 3b2faca..63131e6 100644
--- a/src/include/sdram_mode.h
+++ b/src/include/sdram_mode.h
@@ -50,4 +50,4 @@
#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
-#endif // __SDRAMMODE_H_DEFINED
+#endif /* __SDRAMMODE_H_DEFINED */
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 785ceec..5a9ef37 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) various authors, the coreboot project
*
* This program is free software; you can redistribute it and/or modify
@@ -276,8 +277,7 @@ struct smbios_type2 {
char eos[2];
} __attribute__((packed));
-enum
-{
+enum {
SMBIOS_ENCLOSURE_DESKTOP = 3,
SMBIOS_ENCLOSURE_NOTEBOOK = 9,
};
@@ -472,6 +472,7 @@ struct smbios_type127 {
u8 eos[2];
} __attribute__((packed));
-void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t);
+void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id,
+ struct smbios_type17 *t);
#endif
diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h
index bc50534..56df9f5 100644
--- a/src/include/smp/atomic.h
+++ b/src/include/smp/atomic.h
@@ -29,7 +29,7 @@ typedef struct { int counter; } atomic_t;
* Atomically sets the value of v to i. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
-#define atomic_set(v,i) (((v)->counter) = (i))
+#define atomic_set(v, i) (((v)->counter) = (i))
/**
diff --git a/src/include/spd.h b/src/include/spd.h
index 0bc7898..28eb2f4 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -34,64 +34,99 @@
#define _SPD_H_
/* Byte numbers. */
-#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */
+#define SPD_NUM_MANUFACTURER_BYTES 0 /* Bytes used by module mfg */
#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */
#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */
#define SPD_NUM_ROWS 3 /* Number of row address bits */
-#define SPD_NUM_COLUMNS 4 /* Number of column address bits */
-#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */
+#define SPD_NUM_COLUMNS 4 /* Num of column address bits */
+#define SPD_NUM_DIMM_BANKS 5 /* Num of module rows (banks) */
#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */
#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */
-#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */
-#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
+#define SPD_MODULE_VOLTAGE 8 /* Signal interface levels */
+/* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
+#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
+/* SDRAM access time from clock (highest CAS latency), CAS access time
+ * (Tac, tCAC)
+ */
+#define SPD_ACCESS_TIME_FROM_CLOCK 10
#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */
#define SPD_REFRESH 12 /* Refresh rate/type */
#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */
-#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */
-#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */
-#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */
-#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */
-#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */
-#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */
-#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */
+/* Error checking SDRAM (data) width */
+#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14
+/* SDRAM device attributes, minimum clock delay for back to back random
+ * column
+ */
+#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15
+/* SDRAM device attributes, burst lengths supported */
+#define SPD_SUPPORTED_BURST_LENGTHS 16
+/* SDRAM device attributes, number of banks on SDRAM device */
+#define SPD_NUM_BANKS_PER_SDRAM 17
+/* SDRAM device attributes, CAS latency */
+#define SPD_ACCEPTABLE_CAS_LATENCIES 18
+/* SDRAM device attributes, CS latency */
+#define SPD_CS_LATENCY 19
+/* SDRAM device attributes, WE latency */
+#define SPD_WE_LATENCY 20
#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */
-#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */
-#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */
-#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */
-#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */
-#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */
-#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */
-#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */
-#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */
-#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */
-#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */
-#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */
-#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */
-#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */
-#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
+#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attrs, general */
+/* SDRAM cycle time (2nd highest CAS latency) */
+#define SPD_SDRAM_CYCLE_TIME_2ND 23
+/* SDRAM access from clock (2nd highest CAS latency) */
+#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24
+/* SDRAM cycle time (3rd highest CAS latency) */
+#define SPD_SDRAM_CYCLE_TIME_3RD 25
+/* SDRAM access from clock (3rd highest CAS latency) */
+#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26
+/* Minimum row precharge time (Trp) */
+#define SPD_MIN_ROW_PRECHARGE_TIME 27
+/* Minimum row active to row active (Trrd) */
+#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28
+#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Min RAS to CAS delay (Trcd) */
+#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Min RAS pulse width (Tras) */
+#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Module row density */
+#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Cmd & addr setup time */
+#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Cmd & addr hold time */
+#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data setup time */
+#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data hold time */
#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */
-#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */
-#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */
-#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */
-#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
-#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */
-#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */
-#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */
-#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */
-#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */
+/* Internal write to read command delay (tWTR) */
+#define SPD_INT_WRITE_TO_READ_DELAY 37
+/* Internal read to precharge command delay (tRTP) */
+#define SPD_INT_READ_TO_PRECHARGE_DELAY 38
+/* Memory analysis probe characteristics */
+#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39
+/* Extension of byte 41 (tRC) and byte 42 (tRFC) */
+#define SPD_BYTE_41_42_EXTENSION 40
+/* Minimum active to active auto refresh (tRCmin) */
+#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41
+/* Minimum auto refresh to active/auto refresh (tRFC) */
+#define SPD_MIN_AUTO_REFRESH_TO_ACT 42
+/* Maximum device cycle time (tCKmax) */
+#define SPD_MAX_DEVICE_CYCLE_TIME 43
+/* Maximum skew between DQS and DQ (tDQSQ) */
+#define SPD_MAX_DQS_DQ_SKEW 44
+/* Maximum read data-hold skew factor (tQHS) */
+#define SPD_MAX_READ_DATAHOLD_SKEW 45
#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */
#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
-#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
+/* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
+#define SPD_MANUFACTURER_JEDEC_ID_CODE 64
#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */
-#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
+/* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
+#define SPD_MANUFACTURER_PART_NUMBER 73
#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */
-#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */
-#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */
-#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */
-#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */
-#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
+/* Manufacturing date (byte 93: year, byte 94: week) */
+#define SPD_MANUFACTURING_DATE 93
+/* Assembly serial number (bytes 95-98) */
+#define SPD_ASSEMBLY_SERIAL_NUMBER 95
+/* Manufacturer specific data (bytes 99-125) */
+#define SPD_MANUFACTURER_SPECIFIC_DATA 99
+/* Intel specification for frequency */
+#define SPD_INTEL_SPEC_FOR_FREQUENCY 126
+/* Intel specification details for 100MHz support */
+#define SPD_INTEL_SPEC_100_MHZ 127
/* DRAM specifications use the following naming conventions for SPD locations */
#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME
@@ -100,8 +135,10 @@
#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE
#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME
-#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
-#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+/* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
+#define SPD_tRC 41
+/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+#define SPD_tRFC 42
/* SPD_MEMORY_TYPE values. */
diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h
index d5b2584..47eac52 100644
--- a/src/include/spd_ddr2.h
+++ b/src/include/spd_ddr2.h
@@ -54,7 +54,9 @@
SDRAM device, it could be 0x4, 0x8, so address
lines for that would be 2, and 3 */
-/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr), Height bit[7:5] */
+/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr),
+ * Height bit[7:5]
+ */
#define SPD_MOD_ATTRIB_RANK 5
#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
@@ -72,9 +74,12 @@
#define SPD_RANK_SIZE_256MB (1<<6)
#define SPD_RANK_SIZE_512MB (1<<7)
-#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
-#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */
-#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
+/* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
+#define SPD_DATA_WIDTH 6
+/* Primary SDRAM Width, it could be 0x08 or 0x10 */
+#define SPD_PRI_WIDTH 13
+/* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
+#define SPD_ERR_WIDTH 14
#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */
#define SPD_CAS_LAT_2 (1<<2)
@@ -84,7 +89,10 @@
#define SPD_CAS_LAT_6 (1<<6)
#define SPD_CAS_LAT_7 (1<<7)
-#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */
+/* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2)
+ * + (val & 3) * 0.25)ns
+ */
+#define SPD_TRP 27
#define SPD_TRRD 28
#define SPD_TRCD 29
#define SPD_TRAS 30
@@ -93,7 +101,13 @@
#define SPD_TRTP 38 /* x */
#define SPD_EX_TRC_TRFC 40
-#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
-#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
+/* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)]
+ * ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}
+ */
+#define SPD_TRC 41
+/* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)]
+ * + (val40 & 1)*256
+ */
+#define SPD_TRFC 42
#define SPD_TREF 12
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index d6e7faf..81b805f 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,8 +3,8 @@
#include <stddef.h>
-#define min(a,b) MIN((a),(b))
-#define max(a,b) MAX((a),(b))
+#define min(a, b) MIN((a), (b))
+#define max(a, b) MAX((a), (b))
void *memalign(size_t boundary, size_t size);
void *malloc(size_t size);
diff --git a/src/include/string.h b/src/include/string.h
index f2777a9..a523696 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -16,7 +16,7 @@ void *memset(void *s, int c, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
void *memchr(const void *s, int c, size_t n);
#if !defined(__ROMCC__)
-int snprintf(char * buf, size_t size, const char *fmt, ...);
+int snprintf(char *buf, size_t size, const char *fmt, ...);
#endif
// simple string functions
@@ -24,18 +24,16 @@ int snprintf(char * buf, size_t size, const char *fmt, ...);
static inline size_t strnlen(const char *src, size_t max)
{
size_t i = 0;
- while ((*src++) && (i < max)) {
+ while ((*src++) && (i < max))
i++;
- }
return i;
}
static inline size_t strlen(const char *src)
{
size_t i = 0;
- while (*src++) {
+ while (*src++)
i++;
- }
return i;
}
@@ -70,11 +68,14 @@ static inline char *strconcat(const char *s1, const char *s2)
static inline char *strncpy(char *to, const char *from, int count)
{
+ register char data;
register char *ret = to;
while (count > 0) {
count--;
- if ((*to++ = *from++) == '\0')
+ data = *from++;
+ *to++ = data;
+ if (data == '\0')
break;
}
diff --git a/src/include/swab.h b/src/include/swab.h
index 8a7daba..7d781a0 100644
--- a/src/include/swab.h
+++ b/src/include/swab.h
@@ -21,14 +21,14 @@
#define swab16(x) \
((unsigned short)( \
(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
- (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
+ (((unsigned short)(x) & (unsigned short)0xff00U) >> 8)))
#define swab32(x) \
((unsigned int)( \
- (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
- (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
- (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
- (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
+ (((unsigned int)(x) & 0x000000ffUL) << 24) | \
+ (((unsigned int)(x) & 0x0000ff00UL) << 8) | \
+ (((unsigned int)(x) & 0x00ff0000UL) >> 8) | \
+ (((unsigned int)(x) & 0xff000000UL) >> 24)))
#define swab64(x) \
((uint64_t)( \
@@ -39,6 +39,6 @@
(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \
(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
- (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) ))
+ (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
#endif /* _SWAB_H */
diff --git a/src/include/symbols.h b/src/include/symbols.h
index ea44293..ada7fa7 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -111,6 +111,6 @@ extern u8 _eframebuffer[];
* values from that definition will be used. If not, start, end and size will
* all evaluate to 0. (We can't explicitly assign the symbols to 0 in the
* assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.) */
-#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name )
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name)
#endif /* __SYMBOLS_H */
diff --git a/src/include/thread.h b/src/include/thread.h
index 62f14c2..1906488 100644
--- a/src/include/thread.h
+++ b/src/include/thread.h
@@ -47,10 +47,10 @@ int thread_run(void (*func)(void *), void *arg);
* transitions from occurring in the (state, seq) pair of the boot state
* machine. */
int thread_run_until(void (*func)(void *), void *arg,
- boot_state_t state, boot_state_sequence_t seq);
+ boot_state_t state, boot_state_sequence_t seq);
/* Return 0 on successful yield for the given amount of time, < 0 when thread
* did not yield. */
-int thread_yield_microseconds(unsigned microsecs);
+int thread_yield_microseconds(unsigned int microsecs);
/* Allow and prevent thread cooperation on current running thread. By default
* all threads are marked to be cooperative. That means a thread can yield
@@ -65,16 +65,19 @@ static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci)
}
/* Architecture specific thread functions. */
-void asmlinkage switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack);
+asmlinkage void switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack);
/* Set up the stack frame for a new thread so that a switch_to_thread() call
* will enter the thread_entry() function with arg as a parameter. The
* saved_stack field in the struct thread needs to be updated accordingly. */
void arch_prepare_thread(struct thread *t,
- void asmlinkage (*thread_entry)(void *), void *arg);
+ asmlinkage void (*thread_entry)(void *), void *arg);
#else
static inline void threads_initialize(void) {}
static inline int thread_run(void (*func)(void *), void *arg) { return -1; }
-static inline int thread_yield_microseconds(unsigned microsecs) { return -1; }
+static inline int thread_yield_microseconds(unsigned int microsecs)
+{
+ return -1;
+}
static inline void thread_cooperate(void) {}
static inline void thread_prevent_coop(void) {}
struct cpu_info;
diff --git a/src/include/timer.h b/src/include/timer.h
index 0105e32..9c8beba 100644
--- a/src/include/timer.h
+++ b/src/include/timer.h
@@ -86,7 +86,7 @@ static inline void mono_time_add_msecs(struct mono_time *mt, long ms)
/* Compare two absolute times: Return -1, 0, or 1 if t1 is <, =, or > t2,
* respectively. */
static inline int mono_time_cmp(const struct mono_time *t1,
- const struct mono_time *t2)
+ const struct mono_time *t2)
{
if (t1->microseconds == t2->microseconds)
return 0;
@@ -99,14 +99,14 @@ static inline int mono_time_cmp(const struct mono_time *t1,
/* Return true if t1 after t2 */
static inline int mono_time_after(const struct mono_time *t1,
- const struct mono_time *t2)
+ const struct mono_time *t2)
{
return mono_time_cmp(t1, t2) > 0;
}
/* Return true if t1 before t2. */
static inline int mono_time_before(const struct mono_time *t1,
- const struct mono_time *t2)
+ const struct mono_time *t2)
{
return mono_time_cmp(t1, t2) < 0;
}
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 7e51d80..58edb52 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -18,7 +18,8 @@
#include <commonlib/timestamp_serialized.h>
-#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
+#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT \
+ || !defined(__PRE_RAM__))
/*
* timestamp_init() needs to be called once for each of these cases:
* 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and
diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h
index 95bae77..74cee32 100644
--- a/src/include/tpm_lite/tlcl.h
+++ b/src/include/tpm_lite/tlcl.h
@@ -28,7 +28,7 @@ uint32_t tlcl_lib_init(void);
* Perform a raw TPM request/response transaction.
*/
uint32_t tlcl_send_receive(const uint8_t *request, uint8_t *response,
- int max_length);
+ int max_length);
/* Commands */
@@ -127,7 +127,7 @@ uint32_t tlcl_set_deactivated(uint8_t flag);
* be NULL. The TPM error code is returned.
*/
uint32_t tlcl_get_flags(uint8_t *disable, uint8_t *deactivated,
- uint8_t *nvlocked);
+ uint8_t *nvlocked);
/**
* Set the bGlobalLock flag, which only a reboot can clear. The TPM error
@@ -144,7 +144,7 @@ uint32_t tlcl_lock_nv_write(uint32_t index);
* Perform a TPM_Extend.
*/
uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest,
- uint8_t *out_digest);
+ uint8_t *out_digest);
/**
* Get the entire set of permanent flags.
diff --git a/src/include/tpm_lite/tss_constants.h b/src/include/tpm_lite/tss_constants.h
index eda7d6b..937e553 100644
--- a/src/include/tpm_lite/tss_constants.h
+++ b/src/include/tpm_lite/tss_constants.h
@@ -64,8 +64,7 @@
typedef uint8_t TSS_BOOL;
typedef uint16_t TPM_STRUCTURE_TAG;
-typedef struct tdTPM_PERMANENT_FLAGS
-{
+typedef struct tdTPM_PERMANENT_FLAGS {
TPM_STRUCTURE_TAG tag;
TSS_BOOL disable;
TSS_BOOL ownership;
@@ -89,7 +88,7 @@ typedef struct tdTPM_PERMANENT_FLAGS
TSS_BOOL disableFullDALogicInfo;
} TPM_PERMANENT_FLAGS;
-typedef struct tdTPM_STCLEAR_FLAGS{
+typedef struct tdTPM_STCLEAR_FLAGS {
TPM_STRUCTURE_TAG tag;
TSS_BOOL deactivated;
TSS_BOOL disableForceClear;
diff --git a/src/include/trace.h b/src/include/trace.h
index 362a361..0895084 100644
--- a/src/include/trace.h
+++ b/src/include/trace.h
@@ -27,17 +27,17 @@
#if CONFIG_TRACE && !defined(__SMM__)
-void __cyg_profile_func_enter( void *, void * )
+void __cyg_profile_func_enter(void *, void *)
__attribute__ ((no_instrument_function));
-void __cyg_profile_func_exit( void *, void * )
+void __cyg_profile_func_exit(void *, void *)
__attribute__ ((no_instrument_function));
extern volatile int trace_dis;
-#define DISABLE_TRACE do { trace_dis = 1; } while (0);
-#define ENABLE_TRACE do { trace_dis = 0; } while (0);
-#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function));
+#define DISABLE_TRACE do { trace_dis = 1; } while (0)
+#define ENABLE_TRACE do { trace_dis = 0; } while (0)
+#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function))
#else /* !CONFIG_TRACE */
diff --git a/src/include/vbe.h b/src/include/vbe.h
index 53ea998..7a93775 100644
--- a/src/include/vbe.h
+++ b/src/include/vbe.h
@@ -19,7 +19,9 @@ typedef struct {
u8 display_type; // 0 = NONE, 1 = analog, 2 = digital
u16 screen_width;
u16 screen_height;
- u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width
+ u16 screen_linebytes; /* bytes per line in framebuffer, may be more
+ * than screen_width
+ */
u8 color_depth; // color depth in bits per pixel
u32 framebuffer_address;
u8 edid_block_zero[128];
@@ -40,7 +42,9 @@ typedef struct {
u16 version;
u8 *oem_string_ptr;
u32 capabilities;
- u16 video_mode_list[256]; // lets hope we never have more than 256 video modes...
+ u16 video_mode_list[256]; /* lets hope we never have more than 256
+ * video modes...
+ */
u16 total_memory;
} vbe_info_t;
diff --git a/src/include/watchdog.h b/src/include/watchdog.h
index 8514158..375563d 100644
--- a/src/include/watchdog.h
+++ b/src/include/watchdog.h
@@ -4,7 +4,7 @@
#if CONFIG_USE_WATCHDOG_ON_BOOT
void watchdog_off(void);
#else
-#define watchdog_off() while (0) {}
+#define watchdog_off() { while (0); }
#endif
#endif /* WATCHDOG_H */
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index 2845066..d39f8e2 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -245,9 +245,9 @@ static void cbmemc_reinit(int is_recovery)
init_console_ptr(cbm_cons_p, size, flags);
}
-ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit)
-RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit)
-POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit)
+ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit);
+RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit);
+POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit);
#if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)
void cbmem_dump_console(void)
diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c
index 2a99188..abefd5f 100644
--- a/src/lib/ext_stage_cache.c
+++ b/src/lib/ext_stage_cache.c
@@ -124,6 +124,6 @@ static void stage_cache_setup(int is_recovery)
stage_cache_create_empty();
}
-ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup)
-RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup)
-POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup)
+ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup);
+RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup);
+POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup);
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 2f2a5d8..3b6a01d 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -298,8 +298,8 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery)
ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED;
}
-ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)
-RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)
+ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem);
+RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem);
/* Provide default timestamp implementation using monotonic timer. */
uint64_t __attribute__((weak)) timestamp_get(void)
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index cfb2418..daea18c 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -46,7 +46,7 @@ static void migrate_power_state(int is_recovery)
}
memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
}
-ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
+ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state);
/* Return 0, 3, or 5 to indicate the previous sleep state. */
static int prev_sleep_state(struct chipset_power_state *ps)
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 61851a5..3941adf 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -49,7 +49,7 @@ static void migrate_power_state(int is_recovery)
}
memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
}
-ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
+ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state);
/* Return 0, 3, or 5 to indicate the previous sleep state. */
static uint32_t prev_sleep_state(struct chipset_power_state *ps)
diff --git a/src/vboot/common.c b/src/vboot/common.c
index cfdb82a..f3bde7d 100644
--- a/src/vboot/common.c
+++ b/src/vboot/common.c
@@ -178,5 +178,5 @@ static void vb2_store_selected_region_cbmem(int unused)
{
vb2_store_selected_region();
}
-ROMSTAGE_CBMEM_INIT_HOOK(vb2_store_selected_region_cbmem)
+ROMSTAGE_CBMEM_INIT_HOOK(vb2_store_selected_region_cbmem);
#endif
diff --git a/src/vboot/vboot_handoff.c b/src/vboot/vboot_handoff.c
index 2533a1d..fae462a 100644
--- a/src/vboot/vboot_handoff.c
+++ b/src/vboot/vboot_handoff.c
@@ -185,5 +185,5 @@ static void vb2_fill_handoff_cbmem(int unused)
{
vboot_fill_handoff();
}
-ROMSTAGE_CBMEM_INIT_HOOK(vb2_fill_handoff_cbmem)
+ROMSTAGE_CBMEM_INIT_HOOK(vb2_fill_handoff_cbmem);
#endif
diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c
index d0e2cc1..78b40dd 100644
--- a/src/vendorcode/google/chromeos/cros_vpd.c
+++ b/src/vendorcode/google/chromeos/cros_vpd.c
@@ -223,4 +223,4 @@ char *cros_vpd_gets(const char *key, char *buffer, int size)
return buffer;
}
-RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd)
+RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd);
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