[coreboot-gerrit] Patch set updated for coreboot: reef-on-leaf

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18488

-gerrit

commit ee5d262435b1d1f653a734fc2403af9b9fe3cc23
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Feb 24 10:35:27 2017 -0800

    reef-on-leaf
    
    Change-Id: I6698f747c02af8f51c5f82fe2f457c4d1bce654a
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/mainboard/intel/leafhill/romstage.c | 78 +++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c
index 5c784ba..5cb9c98 100644
--- a/src/mainboard/intel/leafhill/romstage.c
+++ b/src/mainboard/intel/leafhill/romstage.c
@@ -19,6 +19,8 @@
 #include <FspmUpd.h>
 #include "brd_gpio.h"
 
+#include <soc/meminit.h>
+
 static const uint8_t Ch0_Bit_swizzling[] = {
 	0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
 	0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
@@ -44,6 +46,79 @@ static const uint8_t Ch3_Bit_swizzling[] = {
 	0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
 };
 
+const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
+	/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
+	.phys[LP4_PHYS_CH0A] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
+	},
+	.phys[LP4_PHYS_CH0B] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
+	},
+	.phys[LP4_PHYS_CH1A] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
+	},
+	.phys[LP4_PHYS_CH1B] = {
+		/* DQA[0:7] pins of LPDDR4 module. */
+		.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
+		/* DQA[8:15] pins of LPDDR4 module. */
+		.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
+		/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
+		/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+		.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
+	},
+};
+
+/*
+ * The strings in the part_num field aren't necessarily the exact part
+ * numbers used in all the designs. The reason is that the mosys userland
+ * tool uses these strings for dumping more information. Different speed bins
+ * could change in future systems, but the strings still need to match.
+ */
+static const struct lpddr4_sku skus[] = {
+	/*
+	 * K4F6E304HB-MG - both logical channels While the parts
+	 * are listed at 16Gb there are 2 ranks per channel so indicate
+	 * the deneisty as 8Gb per rank.
+	 */
+	[0] = {
+		.speed = LP4_SPEED_2400,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
+		.ch0_dual_rank = 1,
+		.ch1_dual_rank = 1,
+		.part_num = "K4F6E304HB-MGCJ",
+	},
+};
+
+static const struct lpddr4_cfg lp4cfg = {
+	.skus = skus,
+	.num_skus = ARRAY_SIZE(skus),
+	.swizzle_config = &baseboard_lpddr4_swizzle,
+};
+
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	/* setup early gpio before memory */
@@ -116,4 +191,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
 	memupd->FspmConfig.MsgLevelMask = 0x0;
+
+	meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, 0);
+
 }