[coreboot-gerrit] New patch to review for coreboot: mainboard/google/snappy: Override USB2 phy setting

[Wisley Chen (wisley.chen@quantatw.com)]

Wisley Chen (wisley.chen at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18590

-gerrit

commit 125a8c0cdf69556c995dd029393a77ffebda714d
Author: Wisley Chen <wisley.chen at quantatw.com>
Date:   Mon Mar 6 07:00:57 2017 -0500

    mainboard/google/snappy: Override USB2 phy setting
    
    Fine tune USB2, need to override the following registers.
    
    port#1:
      PERPORTPETXISET=7
      PERPORTTXISET=0
    
    BUG=35858164
    BRANCH=reef
    TEST=built, measured eye diagram, and reviewed by intel
    
    Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
    Signed-off-by: Wisley Chen <wisley.chen at quantatw.com>
---
 src/mainboard/google/reef/variants/snappy/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index c83306d..04a5f22 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -112,6 +112,12 @@ chip soc/intel/apollolake
 	# Minimum SLP S3 assertion width 28ms.
 	register "slp_s3_assertion_width_usecs" = "28000"
 
+	# Override USB2 PER PORT register (PORT 1)
+	register "usb2eye[1]" = "{
+		.Usb20PerPortPeTxiSet = 7,
+		.Usb20PerPortTxiSet = 0,
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF