[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI

[Rahul KumarXX Gupta (rahul.kumarxx.gupta@intel.com)]

Rahul KumarXX Gupta (rahul.kumarxx.gupta at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18533

-gerrit

commit 557a233905cfde634eae5957e35289b2c2d4f567
Author: Li Cheng Sooi <li.cheng.sooi at intel.com>
Date:   Fri Feb 24 02:52:13 2017 +0800

    soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI
    
    Add two GPIO macros:
      1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
         APIC with input assuming the events are edge triggered.
    
      2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
         input to SCI assuming the events are level triggered.
    
    Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
    Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta at intel.com>
---
 src/soc/intel/skylake/include/soc/gpio.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 697d3b8..96e0ddb 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -156,12 +156,23 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
 	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \
 		  YES))
 
+/* General purpose input passed through to IOxAPIC. This assumes edge
+ * triggered events. */
+#define PAD_CFG_GPI_APIC_EDGE(pad_, term_, rst_) \
+	_PAD_CFG(pad_, term_, \
+	_DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
+
 /* General purpose input routed to SCI. This assumes edge triggered events. */
 #define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
 	_PAD_CFG_ATTRS(pad_, term_, \
 	_DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \
 		NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
 
+#define PAD_CFG_GPI_ACPI_SCI_LEVEL(pad_, term_, rst_, inv_) \
+	_PAD_CFG_ATTRS(pad_, term_, \
+	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, inv_, \
+		NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI))
+
 /* General purpose input routed to SMI. This assumes edge triggered events. */
 #define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \
 	_PAD_CFG_ATTRS(pad_, term_, \