[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Add SKL SOC PCH H GPIO support
Rahul KumarXX Gupta (rahul.kumarxx.gupta@intel.com)
gerrit at coreboot.org
Mon Mar 6 02:42:46 CET 2017
Rahul KumarXX Gupta (rahul.kumarxx.gupta at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18027
-gerrit
commit a78f4a179ebcf44ecd7075d864c3ec13366f78d4
Author: Li Cheng Sooi <li.cheng.sooi at intel.com>
Date: Wed Jan 4 09:48:39 2017 +0800
soc/intel/skylake: Add SKL SOC PCH H GPIO support
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.
Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.
Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Signed-off-by: Li Cheng Sooi <li.cheng.sooi at intel.com>
Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta at intel.com>
---
src/soc/intel/skylake/acpi/gpio.asl | 21 +++
src/soc/intel/skylake/gpio.c | 13 ++
src/soc/intel/skylake/include/soc/gpio_defs.h | 72 +++-------
.../intel/skylake/include/soc/gpio_pch_h_defs.h | 149 +++++++++++++++++++++
src/soc/intel/skylake/include/soc/gpio_soc_defs.h | 108 +++++++++++++++
5 files changed, 306 insertions(+), 57 deletions(-)
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index c9116d0..0c5a793 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -75,6 +75,26 @@ Device (GPIO)
*/
Method (GADD, 1, NotSerialized)
{
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ /* GPIO Community 0 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
+ {
+ Store (PID_GPIOCOM0, Local0)
+ Subtract (Arg0, GPP_A0, Local1)
+ }
+ /* GPIO Community 1 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23)))
+ {
+ Store (PID_GPIOCOM1, Local0)
+ Subtract (Arg0, GPP_C0, Local1)
+ }
+ /* GPIO Community 03 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10)))
+ {
+ Store (PID_GPIOCOM3, Local0)
+ Subtract (Arg0, GPP_I0, Local1)
+ }
+#else
/* GPIO Community 0 */
If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
{
@@ -93,6 +113,7 @@ Method (GADD, 1, NotSerialized)
Store (PID_GPIOCOM3, Local0)
Subtract (Arg0, GPP_F0, Local1)
}
+#endif /* CONFIG_SKYLAKE_SOC_PCH_H */
Store (PCRB (Local0), Local2)
Add (Local2, PAD_CFG_DW_OFFSET, Local2)
Return (Add (Local2, Multiply (Local1, 8)))
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 6334b3e..f65b1c9 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -45,12 +45,21 @@ static const struct gpio_community communities[] = {
{
.port_id = PID_GPIOCOM1,
.min = GPP_C0,
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ .max = GPP_H23,
+#else
.max = GPP_E23,
+#endif
},
{
.port_id = PID_GPIOCOM3,
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ .min = GPP_I0,
+ .max = GPP_I10,
+#else
.min = GPP_F0,
.max = GPP_G7,
+#endif
},
{
.port_id = PID_GPIOCOM2,
@@ -67,6 +76,10 @@ static const char *gpio_group_names[GPIO_NUM_GROUPS] = {
"GPP_E",
"GPP_F",
"GPP_G",
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+ "GPP_H",
+ "GPP_I",
+#endif
"GPD",
};
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 42a409b..c6e0ab7 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -16,6 +16,12 @@
#ifndef _SOC_GPIO_DEFS_H_
#define _SOC_GPIO_DEFS_H_
+#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
+# include <soc/gpio_pch_h_defs.h>
+#else
+# include <soc/gpio_soc_defs.h>
+#endif
+
/*
* There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case
* where that group is not so generic. So most of the fixed numbers and macros
@@ -29,8 +35,7 @@
#define GPP_E 4
#define GPP_F 5
#define GPP_G 6
-#define GPD 7
-#define GPIO_NUM_GROUPS 8
+
#define GPIO_MAX_NUM_PER_GROUP 24
#define GPIO_DWx_COUNT 2 /* DW0 and DW1 */
@@ -152,64 +157,17 @@
#define GPP_E10 106
#define GPP_E11 107
#define GPP_E12 108
-#define GPP_E13 109
-#define GPP_E14 110
-#define GPP_E15 111
-#define GPP_E16 112
-#define GPP_E17 113
-#define GPP_E18 114
-#define GPP_E19 115
-#define GPP_E20 116
-#define GPP_E21 117
-#define GPP_E22 118
-#define GPP_E23 119
+
+/*
+ * Some of define groups and defines are not generic so defined in
+ * _SOC_GPIO_SOC_DEFS_H and _SOC_GPIO_PCH_H_DEFS_H
+ */
+
/* Group F */
-#define GPP_F0 120
-#define GPP_F1 121
-#define GPP_F2 122
-#define GPP_F3 123
-#define GPP_F4 124
-#define GPP_F5 125
-#define GPP_F6 126
-#define GPP_F7 127
-#define GPP_F8 128
-#define GPP_F9 129
-#define GPP_F10 130
-#define GPP_F11 131
-#define GPP_F12 132
-#define GPP_F13 133
-#define GPP_F14 134
-#define GPP_F15 135
-#define GPP_F16 136
-#define GPP_F17 137
-#define GPP_F18 138
-#define GPP_F19 139
-#define GPP_F20 140
-#define GPP_F21 141
-#define GPP_F22 142
-#define GPP_F23 143
+
/* Group G */
-#define GPP_G0 144
-#define GPP_G1 145
-#define GPP_G2 146
-#define GPP_G3 147
-#define GPP_G4 148
-#define GPP_G5 149
-#define GPP_G6 150
-#define GPP_G7 151
+
/* Group GPD */
-#define GPD0 152
-#define GPD1 153
-#define GPD2 154
-#define GPD3 155
-#define GPD4 156
-#define GPD5 157
-#define GPD6 158
-#define GPD7 159
-#define GPD8 160
-#define GPD9 161
-#define GPD10 162
-#define GPD11 163
/*
* IOxAPIC IRQs for the GPIOs
diff --git a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h
new file mode 100644
index 0000000..54a9978
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_GPIO_PCH_H_DEFS_H_
+#define _SOC_GPIO_PCH_H_DEFS_H_
+
+/*
+ * There are 10 GPIO groups. GPP_A -> GPP_I and GPD. GPD is the special case
+ * where that group is not so generic. So most of the fixed numbers and macros
+ * are based on the GPP groups. The GPIO groups are accessed through register
+ * blocks called communities.
+ */
+
+#define GPP_H 7
+#define GPP_I 8
+#define GPD 9
+#define GPIO_NUM_GROUPS 10
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+/* Group A */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group B */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group C */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group D */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group E */
+/* Some of these are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group F */
+#define GPP_F0 109
+#define GPP_F1 110
+#define GPP_F2 111
+#define GPP_F3 112
+#define GPP_F4 113
+#define GPP_F5 114
+#define GPP_F6 115
+#define GPP_F7 116
+#define GPP_F8 117
+#define GPP_F9 118
+#define GPP_F10 119
+#define GPP_F11 120
+#define GPP_F12 121
+#define GPP_F13 122
+#define GPP_F14 123
+#define GPP_F15 124
+#define GPP_F16 125
+#define GPP_F17 126
+#define GPP_F18 127
+#define GPP_F19 128
+#define GPP_F20 129
+#define GPP_F21 130
+#define GPP_F22 131
+#define GPP_F23 132
+/* Group G */
+#define GPP_G0 133
+#define GPP_G1 134
+#define GPP_G2 135
+#define GPP_G3 136
+#define GPP_G4 137
+#define GPP_G5 138
+#define GPP_G6 139
+#define GPP_G7 140
+#define GPP_G8 141
+#define GPP_G9 142
+#define GPP_G10 143
+#define GPP_G11 144
+#define GPP_G12 145
+#define GPP_G13 146
+#define GPP_G14 147
+#define GPP_G15 148
+#define GPP_G16 149
+#define GPP_G17 150
+#define GPP_G18 151
+#define GPP_G19 152
+#define GPP_G20 153
+#define GPP_G21 154
+#define GPP_G22 155
+#define GPP_G23 156
+/* Group H */
+#define GPP_H0 157
+#define GPP_H1 158
+#define GPP_H2 159
+#define GPP_H3 160
+#define GPP_H4 161
+#define GPP_H5 162
+#define GPP_H6 163
+#define GPP_H7 164
+#define GPP_H8 165
+#define GPP_H9 166
+#define GPP_H10 167
+#define GPP_H11 168
+#define GPP_H12 169
+#define GPP_H13 170
+#define GPP_H14 171
+#define GPP_H15 172
+#define GPP_H16 173
+#define GPP_H17 174
+#define GPP_H18 175
+#define GPP_H19 176
+#define GPP_H20 177
+#define GPP_H21 178
+#define GPP_H22 179
+#define GPP_H23 180
+/* Group I */
+#define GPP_I0 181
+#define GPP_I1 182
+#define GPP_I2 183
+#define GPP_I3 184
+#define GPP_I4 185
+#define GPP_I5 186
+#define GPP_I6 187
+#define GPP_I7 188
+#define GPP_I8 189
+#define GPP_I9 190
+#define GPP_I10 191
+/* Group GPD */
+#define GPD0 192
+#define GPD1 193
+#define GPD2 194
+#define GPD3 195
+#define GPD4 196
+#define GPD5 197
+#define GPD6 198
+#define GPD7 199
+#define GPD8 200
+#define GPD9 201
+#define GPD10 202
+#define GPD11 203
+#endif /* _SOC_GPIO_PCH_H_DEFS_H_ */
diff --git a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000..62e5b5f
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_GPIO_SOC_DEFS_H_
+#define _SOC_GPIO_SOC_DEFS_H_
+
+/*
+ * There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case
+ * where that group is not so generic. So most of the fixed numbers and macros
+ * are based on the GPP groups. The GPIO groups are accessed through register
+ * blocks called communities.
+ */
+
+/* GPP_A -> GPP_G are generic so defined in _SOC_GPIO_DEFS_H_ */
+
+#define GPD 7
+#define GPIO_NUM_GROUPS 8
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+
+/* Group A */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group B */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group C */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group D */
+/* These are generic so defined in _SOC_GPIO_DEFS_H */
+
+/* Group E */
+/* Some of these are generic so defined in _SOC_GPIO_DEFS_H */
+#define GPP_E13 109
+#define GPP_E14 110
+#define GPP_E15 111
+#define GPP_E16 112
+#define GPP_E17 113
+#define GPP_E18 114
+#define GPP_E19 115
+#define GPP_E20 116
+#define GPP_E21 117
+#define GPP_E22 118
+#define GPP_E23 119
+/* Group F */
+#define GPP_F0 120
+#define GPP_F1 121
+#define GPP_F2 122
+#define GPP_F3 123
+#define GPP_F4 124
+#define GPP_F5 125
+#define GPP_F6 126
+#define GPP_F7 127
+#define GPP_F8 128
+#define GPP_F9 129
+#define GPP_F10 130
+#define GPP_F11 131
+#define GPP_F12 132
+#define GPP_F13 133
+#define GPP_F14 134
+#define GPP_F15 135
+#define GPP_F16 136
+#define GPP_F17 137
+#define GPP_F18 138
+#define GPP_F19 139
+#define GPP_F20 140
+#define GPP_F21 141
+#define GPP_F22 142
+#define GPP_F23 143
+/* Group G */
+#define GPP_G0 144
+#define GPP_G1 145
+#define GPP_G2 146
+#define GPP_G3 147
+#define GPP_G4 148
+#define GPP_G5 149
+#define GPP_G6 150
+#define GPP_G7 151
+/* Group GPD */
+#define GPD0 152
+#define GPD1 153
+#define GPD2 154
+#define GPD3 155
+#define GPD4 156
+#define GPD5 157
+#define GPD6 158
+#define GPD7 159
+#define GPD8 160
+#define GPD9 161
+#define GPD10 162
+#define GPD11 163
+
+#endif /* _SOC_GPIO_SOC_DEFS_H_ */
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