[coreboot-gerrit] Patch set updated for coreboot: [RFC] mainboard/sapphire/pureplatinumh61: Add new board
Nicola Corna (nicola@corna.info)
gerrit at coreboot.org
Sun Mar 5 17:40:56 CET 2017
Nicola Corna (nicola at corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18564
-gerrit
commit 7ed3db3e114804183a305eb4996212002c1f6d1c
Author: Nicola Corna <nicola at corna.info>
Date: Fri Mar 3 18:04:48 2017 +0100
[RFC] mainboard/sapphire/pureplatinumh61: Add new board
Add support for Sapphire Pure Platinum H61
This board has a socketed SOIC-8 4 MB flash chip. All the flash
regions are unlocked by default but unfortunately flashrom
doesn't work on this platform; the stock UEFI flash tool refuses
to flash the coreboot image (different image ID), but maybe it
can be spoofed. For now, the external programmer seems to be the
only option.
Everything works well, with the following exceptions:
* The USB 3.0 doesn't work in coreboot (as it is controlled by
a separate PCI controller).
* S3 resume doesn't work (FIXME)
* The raminit is somewhat unstable, as the RAM training
sometimes fails and sometimes succeeds, with the same couple
of DIMMs. (FIXME)
Untested:
* Integrated GPU
* Backside Mini PCI-E port
* Ethernet in coreboot
* Microsoft Windows
Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0
Signed-off-by: Nicola Corna <nicola at corna.info>
---
src/mainboard/sapphire/Kconfig | 16 ++
src/mainboard/sapphire/Kconfig.name | 2 +
src/mainboard/sapphire/pureplatinumh61/Kconfig | 63 +++++++
.../sapphire/pureplatinumh61/Kconfig.name | 2 +
.../sapphire/pureplatinumh61/Makefile.inc | 3 +
src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl | 0
.../sapphire/pureplatinumh61/acpi/platform.asl | 30 ++++
.../sapphire/pureplatinumh61/acpi/superio.asl | 0
.../sapphire/pureplatinumh61/acpi_tables.c | 1 +
.../sapphire/pureplatinumh61/board_info.txt | 6 +
.../sapphire/pureplatinumh61/devicetree.cb | 162 ++++++++++++++++++
src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 46 +++++
.../sapphire/pureplatinumh61/early_southbridge.c | 82 +++++++++
src/mainboard/sapphire/pureplatinumh61/gnvs.c | 34 ++++
src/mainboard/sapphire/pureplatinumh61/gpio.c | 185 +++++++++++++++++++++
src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 87 ++++++++++
src/mainboard/sapphire/pureplatinumh61/mainboard.c | 38 +++++
src/mainboard/sapphire/pureplatinumh61/romstage.c | 1 +
18 files changed, 758 insertions(+)
diff --git a/src/mainboard/sapphire/Kconfig b/src/mainboard/sapphire/Kconfig
new file mode 100644
index 0000000..130c1f4
--- /dev/null
+++ b/src/mainboard/sapphire/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_SAPPHIRE
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/sapphire/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/sapphire/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Sapphire"
+
+endif # VENDOR_SAPPHIRE
diff --git a/src/mainboard/sapphire/Kconfig.name b/src/mainboard/sapphire/Kconfig.name
new file mode 100644
index 0000000..8ea84ad
--- /dev/null
+++ b/src/mainboard/sapphire/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_SAPPHIRE
+ bool "Sapphire"
diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig
new file mode 100644
index 0000000..77ee428
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig
@@ -0,0 +1,63 @@
+if BOARD_SAPPHIRE_PUREPLATINUMH61
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select CPU_INTEL_SOCKET_LGA1155
+ select SUPERIO_FINTEK_F71808A
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select USE_NATIVE_RAMINIT
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default sapphire/pureplatinumh61
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PURE Platinum H61"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0162.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0162"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x1007
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x174b
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 4
+endif
diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig.name b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name
new file mode 100644
index 0000000..7b642bd
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SAPPHIRE_PUREPLATINUMH61
+ bool "Pure Platinum H61"
diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc
new file mode 100644
index 0000000..6064cea
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-y += early_southbridge.c
+romstage-y += gpio.c
+ramstage-y += gnvs.c
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl
new file mode 100644
index 0000000..ef07275
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/sapphire/pureplatinumh61/board_info.txt b/src/mainboard/sapphire/pureplatinumh61/board_info.txt
new file mode 100644
index 0000000..c6360e2
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/board_info.txt
@@ -0,0 +1,6 @@
+Category: mini
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
new file mode 100644
index 0000000..1612188
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -0,0 +1,162 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "0"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "0"
+ register "gpu_dp_c_hotplug" = "0"
+ register "gpu_dp_d_hotplug" = "0"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "0"
+ register "gpu_panel_power_backlight_on_delay" = "0"
+ register "gpu_panel_power_cycle_delay" = "0"
+ register "gpu_panel_power_down_delay" = "0"
+ register "gpu_panel_power_up_delay" = "0"
+ register "gpu_pch_backlight" = "0x00000000"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_LGA1155
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0291"
+ register "gen2_dec" = "0x000c0a01"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x00000000"
+ register "p_cnt_throttling_supported" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x8086 0x1c20
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1c.1 off # PCIe Port #2
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1c.5 on # PCIe Port #6
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x174b 0x1007
+ chip superio/fintek/f71808a
+ register "multi_function_register_1" = "0x00"
+ register "multi_function_register_2" = "0xc4"
+ register "multi_function_register_3" = "0x21"
+ register "multi_function_register_4" = "0x2f"
+ register "multi_function_register_5" = "0x5c"
+ register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V
+ register "hwm_tcc_temp" = "0x66" # TCC temperature = 102 °C
+ register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100%
+ register "hwm_fan1_seg2_speed" = "0xdb" # Fan 1 segment 2 = 86%
+ register "hwm_fan1_seg3_speed" = "0xbc" # Fan 1 segment 3 = 74%
+ register "hwm_fan1_seg4_speed" = "0x9e" # Fan 1 segment 4 = 62%
+ register "hwm_fan1_seg5_speed" = "0x7f" # Fan 1 segment 5 = 50%
+ register "hwm_fan1_temp_src" = "0x18" # Fan 1 source = PECI
+ register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100%
+ register "hwm_fan2_seg2_speed" = "0xdb" # Fan 2 segment 2 = 86%
+ register "hwm_fan2_seg3_speed" = "0xbc" # Fan 2 segment 3 = 74%
+ register "hwm_fan2_seg4_speed" = "0x9e" # Fan 2 segment 4 = 62%
+ register "hwm_fan2_seg5_speed" = "0x7f" # Fan 2 segment 5 = 50%
+ register "hwm_fan2_temp_src" = "0x1e" # Fan 2 source = temperature 2
+ device pnp 4e.1 off end # Serial Port 1
+ device pnp 4e.4 on # Hardware monitor
+ io 0x60 = 0x295
+ irq 0x70 = 0
+ end
+ device pnp 4e.5 off end # Keyboard
+ device pnp 4e.6 on # GPIO
+ io 0xc5 = 0x1f
+ end
+ device pnp 4e.7 on # WDT
+ io 0x60 = 0xa00
+ end
+ device pnp 4e.8 off end # CIR
+ device pnp 4e.a off end # PME, ACPI, EUP
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x174b 0x1007
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x174b 0x1007
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics
+ subsystemid 0x174b 0x1007
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x8086 0x2010
+ end
+ end
+end
diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl
new file mode 100644
index 0000000..eb98bb2
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+ }
+ }
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c
new file mode 100644
index 0000000..d9c5ee9
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+}
+
+void rcba_config(void)
+{
+ /* Disable devices. */
+ RCBA32(0x3414) = 0x00000020;
+ RCBA32(0x3418) = 0x1fce1fe3;
+
+}
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/gnvs.c b/src/mainboard/sapphire/pureplatinumh61/gnvs.c
new file mode 100644
index 0000000..a790b0b
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/gnvs.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c
new file mode 100644
index 0000000..5d66f47
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c
@@ -0,0 +1,185 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio6 = GPIO_DIR_OUTPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio6 = GPIO_LEVEL_LOW,
+ .gpio9 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio6 = GPIO_NO_BLINK,
+ .gpio9 = GPIO_NO_BLINK,
+ .gpio15 = GPIO_NO_BLINK,
+ .gpio22 = GPIO_NO_BLINK,
+ .gpio24 = GPIO_NO_BLINK,
+ .gpio25 = GPIO_NO_BLINK,
+ .gpio26 = GPIO_NO_BLINK,
+ .gpio27 = GPIO_NO_BLINK,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio10 = GPIO_NO_INVERT,
+ .gpio12 = GPIO_NO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_NO_INVERT,
+ .gpio28 = GPIO_NO_INVERT,
+ .gpio29 = GPIO_NO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio6 = GPIO_RESET_PWROK,
+ .gpio7 = GPIO_RESET_PWROK,
+ .gpio8 = GPIO_RESET_PWROK,
+ .gpio9 = GPIO_RESET_PWROK,
+ .gpio10 = GPIO_RESET_PWROK,
+ .gpio12 = GPIO_RESET_PWROK,
+ .gpio13 = GPIO_RESET_PWROK,
+ .gpio14 = GPIO_RESET_PWROK,
+ .gpio15 = GPIO_RESET_PWROK,
+ .gpio22 = GPIO_RESET_PWROK,
+ .gpio23 = GPIO_RESET_PWROK,
+ .gpio24 = GPIO_RESET_PWROK,
+ .gpio25 = GPIO_RESET_PWROK,
+ .gpio26 = GPIO_RESET_PWROK,
+ .gpio27 = GPIO_RESET_PWROK,
+ .gpio28 = GPIO_RESET_PWROK,
+ .gpio29 = GPIO_RESET_PWROK,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_LOW,
+ .gpio39 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+ .gpio35 = GPIO_RESET_PWROK,
+ .gpio37 = GPIO_RESET_PWROK,
+ .gpio38 = GPIO_RESET_PWROK,
+ .gpio39 = GPIO_RESET_PWROK,
+ .gpio48 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_reset = {
+ .gpio68 = GPIO_RESET_PWROK,
+ .gpio69 = GPIO_RESET_PWROK,
+ .gpio72 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c
new file mode 100644
index 0000000..cf723d0
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */
+ 0x10ec0000, /* Subsystem ID */
+
+ 0x0000000f, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x2, 0x10ec0000),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+
+ /* NID 0x14. */
+ AZALIA_PIN_CFG(0x2, 0x14, 0x01014c10),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x2, 0x15, 0x01011c12),
+
+ /* NID 0x16. */
+ AZALIA_PIN_CFG(0x2, 0x16, 0x01016c11),
+
+ /* NID 0x17. */
+ AZALIA_PIN_CFG(0x2, 0x17, 0x01012c14),
+
+ /* NID 0x18. */
+ AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c40),
+
+ /* NID 0x19. */
+ AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c50),
+
+ /* NID 0x1a. */
+ AZALIA_PIN_CFG(0x2, 0x1a, 0x01813c4f),
+
+ /* NID 0x1b. */
+ AZALIA_PIN_CFG(0x2, 0x1b, 0x0321403f),
+
+ /* NID 0x1c. */
+ AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
+
+ /* NID 0x1d. */
+ AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601),
+
+ /* NID 0x1e. */
+ AZALIA_PIN_CFG(0x2, 0x1e, 0x0145e130),
+
+ /* NID 0x1f. */
+ AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c
new file mode 100644
index 0000000..83cfd76
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_init(device_t dev)
+{
+ RCBA32(0x38c8) = 0x00002009;
+ RCBA32(0x38c4) = 0x00802009;
+ RCBA32(0x38c0) = 0x00000007;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
new file mode 100644
index 0000000..f1839f0
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -0,0 +1 @@
+/* dummy file */
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