[coreboot-gerrit] Patch set updated for coreboot: nb/x4x: Disable IGD when external GPU is found

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504

-gerrit

commit 9c09a6fc2c3369755a17b670b98d61ce90d01905
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Sun Feb 26 23:04:51 2017 +0100

    nb/x4x: Disable IGD when external GPU is found
    
    This disables IGD before raminit if an external GPU is found unless
    CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
    
    TESTED on ga-g41m-es2l
    
    Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/x4x/early_init.c | 25 +++++++++++++++++++++++++
 src/northbridge/intel/x4x/x4x.h        |  1 +
 2 files changed, 26 insertions(+)

diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 7d6afc9..dfa90cc 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -24,10 +24,12 @@
 #include <console/console.h>
 #include <halt.h>
 #include <romstage_handoff.h>
+#include <device/pci_def.h>
 
 void x4x_early_init(void)
 {
 	const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
+	u32 reg32;
 
 	/* Setup MCHBAR. */
 	pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
@@ -64,6 +66,29 @@ void x4x_early_init(void)
 		gfxsize = 6;
 	}
 	pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4));
+
+	/*
+	 * Disabling IGD later is possible but somehow reclaiming its UMA
+	 * resources fails so enable/disable IGD before raminit if external
+	 * GPU is found.
+	 * NOTE: PCI specifies that one needs to wait at least 100msec after
+	 * reset. In practise GPUs seem to get detected fine without this.
+	 */
+	if (pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS) & (1 << 6) &&
+		!IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY)) {
+		pci_write_config8(PCI_DEV(0, 0x01, 0), PCI_SECONDARY_BUS, 0x0a);
+		pci_write_config8(PCI_DEV(0, 0x01, 0),
+				PCI_SUBORDINATE_BUS, 0x0a);
+		reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
+		if (reg32 == 0x030000) {
+			printk(BIOS_DEBUG,"External GPU is found."
+				" xDisabling IGD before raminit\n");
+			reg32 = pci_read_config32(d0f0, D0F0_DEVEN);
+			pci_write_config32(d0f0, D0F0_DEVEN,
+					reg32 & ~(IGD0EN | IGD1EN));
+			pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
+		}
+	}
 }
 
 static void init_egress(void)
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index faae775..834128b 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -60,6 +60,7 @@
  */
 #define PEG_CAP 0xa2
 #define SLOTCAP 0xb4
+#define SLOTSTS 0xba
 #define PEGLC 0xec
 #define D1F0_VCCAP 0x104
 #define D1F0_VC0RCTL 0x114