[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Clean up Systemagent code
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Sun Mar 5 13:11:42 CET 2017
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18567
-gerrit
commit 068c2da1b1ad2bc9b3d6a5ff623b1aa432cb7681
Author: Subrata Banik <subrata.banik at intel.com>
Date: Sat Mar 4 23:39:47 2017 +0530
soc/intel/apollolake: Clean up Systemagent code
Use common systemagent header.
Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/soc/intel/apollolake/Kconfig | 4 ---
src/soc/intel/apollolake/bootblock/bootblock.c | 2 +-
src/soc/intel/apollolake/chip.c | 2 +-
src/soc/intel/apollolake/include/soc/iomap.h | 2 ++
src/soc/intel/apollolake/include/soc/northbridge.h | 40 ----------------------
src/soc/intel/apollolake/memmap.c | 2 +-
src/soc/intel/apollolake/northbridge.c | 2 +-
src/soc/intel/apollolake/romstage.c | 2 +-
8 files changed, 7 insertions(+), 49 deletions(-)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 4ff64d2..0322318 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -88,10 +88,6 @@ config SOC_INTEL_COMMON_RESET
bool
default y
-config MMCONF_BASE_ADDRESS
- hex "PCI MMIO Base Address"
- default 0xe0000000
-
config IOSF_BASE_ADDRESS
hex "MMIO Base Address of sideband bus"
default 0xd0000000
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 1f5055d..4f4e25f 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -18,6 +18,7 @@
#include <bootblock_common.h>
#include <cpu/x86/mtrr.h>
#include <device/pci.h>
+#include <intelblocks/systemagent.h>
#include <lib.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
@@ -25,7 +26,6 @@
#include <soc/gpio.h>
#include <soc/iosf.h>
#include <soc/mmap_boot.h>
-#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/uart.h>
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1de41cf..5383082 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <intelblocks/systemagent.h>
#include <romstage_handoff.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
@@ -37,7 +38,6 @@
#include <spi-generic.h>
#include <soc/pm.h>
#include <soc/p2sb.h>
-#include <soc/northbridge.h>
#include "chip.h"
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 3c94d1b..5e65592 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -25,6 +25,8 @@
#define MCH_BASE_ADDR 0xfed10000
#define MCH_BASE_SIZE (32 * KiB)
+#define PCIEX_SIZE (256 * MiB)
+
#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168
#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078
#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
deleted file mode 100644
index 04e369e..0000000
--- a/src/soc/intel/apollolake/include/soc/northbridge.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
-#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
-
-#define MCHBAR 0x48
-#define PCIEXBAR 0x60
-#define PCIEX_SIZE (256 * MiB)
-
-#define BDSM 0xb0 /* Base Data Stolen Memory */
-#define BGSM 0xb4 /* Base GTT Stolen Memory */
-#define TSEG 0xb8 /* TSEG base */
-#define TOLUD 0xbc /* Top of Low Used Memory */
-#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
-
-/* IMR registers are found under MCHBAR. */
-#define MCHBAR_IMR0BASE 0x6870
-#define MCHBAR_IMR0MASK 0x6874
-#define MCH_IMR_PITCH 0x20
-#define MCH_NUM_IMRS 20
-
-/* RAPL Package Power Limit register under MCHBAR. */
-#define MCHBAR_RAPL_PPL 0x70A8
-
-#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index cccbffd..4a43136 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -27,7 +27,7 @@
#include <assert.h>
#include <cbmem.h>
#include <device/pci.h>
-#include <soc/northbridge.h>
+#include <intelblocks/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/smm.h>
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
index cc097ba..855df09 100644
--- a/src/soc/intel/apollolake/northbridge.c
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -20,7 +20,7 @@
#include <soc/iomap.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <soc/northbridge.h>
+#include <intelblocks/systemagent.h>
#include <soc/pci_ids.h>
static uint32_t get_bar(device_t dev, unsigned int index)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 97be0f6..5195909 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -31,11 +31,11 @@
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
+#include <intelblocks/systemagent.h>
#include <soc/cpu.h>
#include <soc/flash_ctrlr.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
-#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
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