[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common/block: [WIP]Add Intel common systemagent support

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18454

-gerrit

commit 0a6800a04f60e46a48a9a741c6a2ce95bcbef5bc
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Sun Mar 5 13:19:42 2017 +0530

    soc/intel/common/block: [WIP]Add Intel common systemagent support
    
    Create common Intel systemagent code.
    This code currently contains the SA initialization
    required in Bootblock phase, which has the following programming-
    * Set PCIEXBAR
    * Clear TSEG register
    More code will get added up in the subsequent phases.
    
    Change-Id: Ib8a77aec8b20bafd4175048d442701250f1aa9c8
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/common/block/systemagent/Kconfig     | 27 +++++++++++++++
 .../intel/common/block/systemagent/Makefile.inc    |  1 +
 .../intel/common/block/systemagent/systemagent.c   | 39 ++++++++++++++++++++++
 3 files changed, 67 insertions(+)

diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
new file mode 100644
index 0000000..75ec6aa
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -0,0 +1,27 @@
+config SOC_INTEL_COMMON_BLOCK_SA
+	bool
+	help
+	  Intel Processor common System Agent support
+
+config PCIEX_BASE_ADDRESS
+        hex
+        default 0xe0000000
+
+config SA_PCIEX_LENGTH
+	hex
+	default PCIEX_LENGTH_256MB if (SOC_INTEL_CAR_SMALL_CORE)
+	default PCIEX_LENGTH_64MB if (SOC_INTEL_CAR_BIG_CORE)
+	help
+	  This option allows you to select length of PCIEX region.
+
+config PCIEX_LENGTH_256MB
+	hex
+	default 0x0
+
+config PCIEX_LENGTH_128MB
+	hex
+	default 0x2
+
+config PCIEX_LENGTH_64MB
+	hex
+	default 0x4
diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc
new file mode 100644
index 0000000..75d5626
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Makefile.inc
@@ -0,0 +1 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
new file mode 100644
index 0000000..7c356f9
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <intelblocks/systemagent.h>
+
+void bootblock_systemagent_early_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+	reg = CONFIG_PCIEX_BASE_ADDRESS | CONFIG_SA_PCIEX_LENGTH | 1;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+
+	/*
+	 * Clear TSEG register - TSEG register comes out of reset with a
+	 * non-zero default value. Clear this register to ensure that there are
+	 * no surprises in CBMEM handling.
+	 */
+	pci_io_write_config32(SA_DEV_ROOT, TSEG, 0);
+}
+