[coreboot-gerrit] Patch set updated for coreboot: intelblocks/systemagent: Create header for host bridge B0:D0:F0 registers

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18565

-gerrit

commit 21487e54b99ebf73d88313332630462e0de48259
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Sat Mar 4 23:32:41 2017 +0530

    intelblocks/systemagent: Create header for host bridge B0:D0:F0 registers
    
    Move all common registers and specific to SOC registers into
    a common location to avoid duplication.
    
    Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 .../common/block/include/intelblocks/systemagent.h | 129 +++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
new file mode 100644
index 0000000..ab09fb2
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_SA_H
+#define SOC_INTEL_COMMON_SA_H
+
+#include <intelblocks/pci_devs.h>
+
+/* System Agent Devices */
+#define SA_DEV_SLOT_ROOT     0x00
+#define SA_DEVFN_ROOT        _SA_DEVFN(ROOT)
+#define SA_DEV_ROOT          _SA_DEV(ROOT)
+
+/* Device 0:0.0 PCI configuration space */
+
+#define MCHBAR          0x48
+#define PCIEXBAR        0x60
+#define GGC             0x50
+
+#define TOUUD           0xa8    /* Top of Upper Usable DRAM */
+#define BDSM            0xb0    /* Base Data Stolen Memory */
+#define BGSM            0xb4    /* Base GTT Stolen Memory */
+#define TSEG            0xb8    /* TSEG base */
+#define TOLUD           0xbc    /* Top of Low Used Memory */
+
+#if IS_ENABLED(CONFIG_SOC_INTEL_CAR_SMALL_CORE)
+
+/* Device 0:0.0 PCI configuration space */
+#define DEVEN           0x54
+#define  DEVEN_D3EN     (1 << 5)
+#define  DEVEN_D2EN     (1 << 4)
+#define  DEVEN_D0F1EN   (1 << 1)
+#define  DEVEN_D0EN     (1 << 0)
+
+/* MCHBAR */
+
+/* IMR registers are found under MCHBAR. */
+#define MCHBAR_IMR0BASE         0x6870
+#define MCHBAR_IMR0MASK         0x6874
+#define MCH_IMR_PITCH           0x20
+#define MCH_NUM_IMRS            20
+/* RAPL Package Power Limit register under MCHBAR. */
+#define MCHBAR_RAPL_PPL         0x70A8
+
+#elif IS_ENABLED(CONFIG_SOC_INTEL_CAR_BIG_CORE)
+
+/* Device 0:0.0 PCI configuration space */
+#define EPBAR           0x40
+#define DMIBAR          0x68
+#define DEVEN           0x54
+#define  DEVEN_D7EN     (1 << 14)
+#define  DEVEN_D4EN     (1 << 7)
+#define  DEVEN_D3EN     (1 << 5)
+#define  DEVEN_D2EN     (1 << 4)
+#define  DEVEN_D1F0EN   (1 << 3)
+#define  DEVEN_D1F1EN   (1 << 2)
+#define  DEVEN_D1F2EN   (1 << 1)
+#define  DEVEN_D0EN     (1 << 0)
+#define DPR             0x5c
+#define  DPR_EPM        (1 << 2)
+#define  DPR_PRS        (1 << 1)
+#define  DPR_SIZE_MASK  0xff0
+
+#define PAM0            0x80
+#define PAM1            0x81
+#define PAM2            0x82
+#define PAM3            0x83
+#define PAM4            0x84
+#define PAM5            0x85
+#define PAM6            0x86
+
+#define SMRAM           0x88    /* System Management RAM Control */
+#define  D_OPEN         (1 << 6)
+#define  D_CLS          (1 << 5)
+#define  D_LCK          (1 << 4)
+#define  G_SMRAME       (1 << 3)
+#define  C_BASE_SEG     ((0 << 2) | (1 << 1) | (0 << 0))
+
+#define MESEG_BASE      0x70    /* Management Engine Base. */
+#define MESEG_LIMIT     0x78    /* Management Engine Limit. */
+#define REMAPBASE       0x90    /* Remap base. */
+#define REMAPLIMIT      0x98    /* Remap limit. */
+#define TOM             0xa0    /* Top of DRAM in memory controller space. */
+
+/* MCHBAR */
+
+#define MCHBAR_PEI_VERSION      0x5034
+#define BIOS_RESET_CPL          0x5da8
+#define EDRAMBAR                0x5408
+#define MCH_PAIR                0x5418
+#define GDXCBAR                 0x5420
+
+#define MCH_PKG_POWER_LIMIT_LO  0x59a0
+#define MCH_PKG_POWER_LIMIT_HI  0x59a4
+#define MCH_DDR_POWER_LIMIT_LO  0x58e0
+#define MCH_DDR_POWER_LIMIT_HI  0x58e4
+
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE                  0x5da4
+#define  MAILBOX_RUN_BUSY                       (1 << 31)
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE                0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND     1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT             2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA        3
+#define  MAILBOX_BIOS_ERROR_RESERVED            4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID       5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR            7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA                       0x5da0
+
+#endif
+
+void bootblock_systemagent_early_init(void);
+
+#endif	/* SOC_INTEL_COMMON_SA_H */