[coreboot-gerrit] Patch set updated for coreboot: Stage rules.h: Add ENV_LIBAGESA

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18544

-gerrit

commit ba8f1f0d12b2a8ebc227c84af0696e6ed0b184be
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Mar 2 13:01:58 2017 +0200

    Stage rules.h: Add ENV_LIBAGESA
    
    Definition is required to enable use of printk() from AGESA proper.
    
    Change-Id: I6666a003c91794490f670802d496321ffb965cd3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/include/rules.h                   | 23 ++++++++++++++++++++---
 src/vendorcode/amd/agesa/Makefile.inc |  1 +
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index a632804..0f21231 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -27,6 +27,7 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "bootblock"
 
 #elif defined(__ROMSTAGE__)
@@ -37,6 +38,7 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "romstage"
 
 #elif defined(__SMM__)
@@ -47,6 +49,7 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "smm"
 
 #elif defined(__VERSTAGE__)
@@ -57,6 +60,7 @@
 #define ENV_VERSTAGE 1
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "verstage"
 
 #elif defined(__RAMSTAGE__)
@@ -67,6 +71,7 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "ramstage"
 
 #elif defined(__RMODULE__)
@@ -77,6 +82,7 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 1
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "rmodule"
 
 #elif defined(__POSTCAR__)
@@ -87,14 +93,24 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 1
+#define ENV_LIBAGESA 0
 #define ENV_STRING "postcar"
 
+#elif defined(__LIBAGESA__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_VERSTAGE 0
+#define ENV_RMODULE 0
+#define ENV_POSTCAR 0
+#define ENV_LIBAGESA 1
+#define ENV_STRING "libagesa"
+
 #else
 /*
  * Default case of nothing set for random blob generation using
- * create_class_compiler that isn't bound to a stage. Also AGESA
- * apparently builds things compeletely separate from coreboot's
- * build infrastructure -- hardcoding its own rules.
+ * create_class_compiler that isn't bound to a stage.
  */
 #define ENV_BOOTBLOCK 0
 #define ENV_ROMSTAGE 0
@@ -103,6 +119,7 @@
 #define ENV_VERSTAGE 0
 #define ENV_RMODULE 0
 #define ENV_POSTCAR 0
+#define ENV_LIBAGESA 0
 #define ENV_STRING "UNKNOWN"
 #endif
 
diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
index fab6f63..f2423d0 100644
--- a/src/vendorcode/amd/agesa/Makefile.inc
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -12,6 +12,7 @@ subdirs-y += common
 
 classes-y += libagesa
 libagesa-y =
+libagesa-generic-ccopts += -D__LIBAGESA__
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
 $(eval $(call create_class_compiler,libagesa,x86_32))