[coreboot-gerrit] Patch set updated for coreboot: [NOTFORMERGE] agesa-wrapper-killer
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sat Mar 4 08:01:34 CET 2017
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18477
-gerrit
commit c1d26ee262f0b753bc8db441b76171f7dd51a9ff
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Feb 23 20:50:53 2017 +0200
[NOTFORMERGE] agesa-wrapper-killer
Change-Id: I5fcfed645ccc6f3c78b5050535d97dc95e82ed94
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/agesa/Makefile.inc | 2 +-
src/cpu/amd/agesa/amd_late_init.c | 42 ---
src/cpu/amd/agesa/cache_as_ram.inc | 92 +++---
src/cpu/amd/agesa/family12/Makefile.inc | 1 +
src/cpu/amd/agesa/family12/romstage.c | 36 +++
src/cpu/amd/agesa/family14/Makefile.inc | 1 +
src/cpu/amd/agesa/family14/romstage.c | 31 ++
src/cpu/amd/agesa/family15/Makefile.inc | 1 +
src/cpu/amd/agesa/family15/romstage.c | 55 ++++
src/cpu/amd/agesa/family15rl/Makefile.inc | 1 +
src/cpu/amd/agesa/family15rl/romstage.c | 28 ++
src/cpu/amd/agesa/family15tn/Makefile.inc | 1 +
src/cpu/amd/agesa/family15tn/romstage.c | 28 ++
src/cpu/amd/agesa/family16kb/Makefile.inc | 1 +
src/cpu/amd/agesa/family16kb/romstage.c | 28 ++
src/cpu/amd/agesa/romstage.c | 111 +++++++
src/cpu/amd/agesa/s3_resume.c | 44 +--
src/cpu/amd/agesa/s3_resume.h | 2 +-
src/include/cpu/amd/car.h | 30 ++
src/mainboard/amd/dinar/OemCustomize.c | 17 +-
src/mainboard/amd/dinar/romstage.c | 69 +---
src/mainboard/amd/inagua/OemCustomize.c | 16 +-
src/mainboard/amd/inagua/romstage.c | 64 +---
src/mainboard/amd/olivehill/OemCustomize.c | 26 +-
src/mainboard/amd/olivehill/mainboard.c | 3 -
src/mainboard/amd/olivehill/romstage.c | 79 +----
src/mainboard/amd/parmer/OemCustomize.c | 26 +-
src/mainboard/amd/parmer/mainboard.c | 3 -
src/mainboard/amd/parmer/romstage.c | 59 +---
src/mainboard/amd/persimmon/OemCustomize.c | 16 +-
src/mainboard/amd/persimmon/romstage.c | 81 +----
src/mainboard/amd/south_station/OemCustomize.c | 16 +-
src/mainboard/amd/south_station/romstage.c | 62 +---
src/mainboard/amd/thatcher/OemCustomize.c | 26 +-
src/mainboard/amd/thatcher/mainboard.c | 3 -
src/mainboard/amd/thatcher/romstage.c | 79 +----
src/mainboard/amd/torpedo/OemCustomize.c | 16 +-
src/mainboard/amd/torpedo/romstage.c | 74 +----
src/mainboard/amd/union_station/OemCustomize.c | 16 +-
src/mainboard/amd/union_station/romstage.c | 64 +---
src/mainboard/asrock/e350m1/OemCustomize.c | 16 +-
src/mainboard/asrock/e350m1/romstage.c | 80 +----
src/mainboard/asrock/imb-a180/OemCustomize.c | 27 +-
src/mainboard/asrock/imb-a180/mainboard.c | 3 -
src/mainboard/asrock/imb-a180/romstage.c | 85 +----
src/mainboard/asus/f2a85-m/OemCustomize.c | 27 +-
src/mainboard/asus/f2a85-m/mainboard.c | 3 -
src/mainboard/asus/f2a85-m/romstage.c | 152 +++------
src/mainboard/asus/f2a85-m_le/OemCustomize.c | 2 +-
src/mainboard/bap/ode_e20XX/OemCustomize.c | 26 +-
src/mainboard/bap/ode_e20XX/mainboard.c | 3 -
src/mainboard/bap/ode_e20XX/romstage.c | 80 +----
src/mainboard/biostar/am1ml/OemCustomize.c | 26 +-
src/mainboard/biostar/am1ml/mainboard.c | 3 -
src/mainboard/biostar/am1ml/romstage.c | 107 ++-----
src/mainboard/elmex/pcm205400/OemCustomize.c | 16 +-
src/mainboard/elmex/pcm205400/romstage.c | 82 +----
src/mainboard/gizmosphere/gizmo/OemCustomize.c | 16 +-
src/mainboard/gizmosphere/gizmo/romstage.c | 79 +----
src/mainboard/gizmosphere/gizmo2/OemCustomize.c | 26 +-
src/mainboard/gizmosphere/gizmo2/mainboard.c | 4 -
src/mainboard/gizmosphere/gizmo2/romstage.c | 81 +----
src/mainboard/hp/abm/OemCustomize.c | 26 +-
src/mainboard/hp/abm/mainboard.c | 3 -
src/mainboard/hp/abm/romstage.c | 80 ++---
src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c | 26 +-
src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 5 +-
src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 70 +---
src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | 16 +-
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 95 +-----
src/mainboard/lenovo/g505s/OemCustomize.c | 26 +-
src/mainboard/lenovo/g505s/mainboard.c | 4 +-
src/mainboard/lenovo/g505s/romstage.c | 69 +---
.../lippert/frontrunner-af/OemCustomize.c | 16 +-
src/mainboard/lippert/frontrunner-af/romstage.c | 79 +----
src/mainboard/lippert/toucan-af/OemCustomize.c | 16 +-
src/mainboard/lippert/toucan-af/romstage.c | 78 +----
src/mainboard/msi/ms7721/OemCustomize.c | 27 +-
src/mainboard/msi/ms7721/mainboard.c | 3 -
src/mainboard/msi/ms7721/romstage.c | 135 +++-----
src/mainboard/pcengines/apu1/OemCustomize.c | 16 +-
src/mainboard/pcengines/apu1/romstage.c | 92 +-----
src/mainboard/supermicro/h8qgi/OemCustomize.c | 16 +-
src/mainboard/supermicro/h8qgi/romstage.c | 59 +---
src/mainboard/supermicro/h8scm/OemCustomize.c | 18 +-
src/mainboard/supermicro/h8scm/romstage.c | 75 +----
src/mainboard/tyan/s8226/OemCustomize.c | 16 +-
src/mainboard/tyan/s8226/romstage.c | 57 +---
src/northbridge/amd/agesa/Makefile.inc | 7 +-
src/northbridge/amd/agesa/agesawrapper.c | 352 ---------------------
src/northbridge/amd/agesa/agesawrapper.h | 27 +-
src/northbridge/amd/agesa/eventlog.c | 34 ++
src/northbridge/amd/agesa/family12/Makefile.inc | 3 +
src/northbridge/amd/agesa/family12/northbridge.c | 19 --
src/northbridge/amd/agesa/family12/state_machine.c | 77 +++++
src/northbridge/amd/agesa/family14/Makefile.inc | 3 +
src/northbridge/amd/agesa/family14/northbridge.c | 25 --
src/northbridge/amd/agesa/family14/state_machine.c | 84 +++++
src/northbridge/amd/agesa/family15/northbridge.c | 16 -
src/northbridge/amd/agesa/family15/state_machine.c | 51 +++
src/northbridge/amd/agesa/family15rl/Makefile.inc | 3 +
src/northbridge/amd/agesa/family15rl/northbridge.c | 16 -
.../amd/agesa/family15rl/state_machine.c | 81 +++++
src/northbridge/amd/agesa/family15tn/Makefile.inc | 3 +
src/northbridge/amd/agesa/family15tn/northbridge.c | 16 -
.../amd/agesa/family15tn/state_machine.c | 80 +++++
src/northbridge/amd/agesa/family16kb/Makefile.inc | 3 +
src/northbridge/amd/agesa/family16kb/northbridge.c | 16 -
.../amd/agesa/family16kb/state_machine.c | 81 +++++
src/northbridge/amd/agesa/state_machine.c | 341 ++++++++++++++++++++
src/northbridge/amd/agesa/state_machine.h | 70 ++++
src/southbridge/amd/agesa/hudson/agesawrapper.c | 13 -
src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +-
src/vendorcode/amd/agesa/f16kb/gcccar.inc | 3 +-
114 files changed, 1944 insertions(+), 2899 deletions(-)
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 60bae12..b9dae57 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -24,10 +24,10 @@ romstage-y += s3_resume.c
ramstage-y += s3_mtrr.c
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
+romstage-y += romstage.c
romstage-y += heapmanager.c
ramstage-y += heapmanager.c
-ramstage-y += amd_late_init.c
ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
deleted file mode 100644
index a55ebd8..0000000
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <bootstate.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#if CONFIG_AMD_SB_CIMX
-#include <sb_cimx.h>
-#endif
-
-static void agesawrapper_post_device(void *unused)
-{
- if (acpi_is_wakeup_s3())
- return;
-
- agesawrapper_amdinitlate();
-
-#if CONFIG_AMD_SB_CIMX
- sb_Late_Post();
-#endif
- if (!acpi_s3_resume_allowed())
- return;
-
- agesawrapper_amdS3Save();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
- agesawrapper_post_device, NULL);
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 24db600..f43e6a4 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -26,43 +26,24 @@
#include "gcccar.inc"
#include <cpu/x86/cache.h>
-/*
- * XMM map:
- * xmm0: BIST
- * xmm1: backup ebx -- cpu_init_detected
- */
-
.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+.globl cache_as_ram_setup, cache_as_ram_setup_out
cache_as_ram_setup:
- post_code(0xa0)
-
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3<<9), %eax
- movl %eax, %cr4
-
- /* Get the cpu_init_detected */
- mov $1, %eax
- cpuid
- shr $24, %ebx
-
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
- /* for normal part %ebx already contain cpu_init_detected from fallback call */
+ /* Preserve BIST. */
+ movl %eax, %ebp
- /* Save the cpu_init_detected */
- cvtsi2sd %ebx, %xmm1
+ post_code(0xa0)
post_code(0xa1)
+ /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
AMD_ENABLE_STACK
+ /* Align the stack to 128 bits. No harm on i386, required on x86_64? */
+ and $0xFFFFFFF0, %esp
+
#ifdef __x86_64__
/* switch to 64 bit long mode */
mov %esi, %ecx
@@ -105,42 +86,36 @@ cache_as_ram_setup:
# use call far to switch to 64-bit code segment
ljmp $0x18, $1f
1:
- /* Pass the cpu_init_detected */
- cvtsd2si %xmm1, %esi
- /* Pass the BIST result */
- cvtsd2si %xmm0, %edi
+ .code64
+
+ /* Calling conventions preserve BIST in %ebp. */
- /* align the stack */
- and $0xFFFFFFF0, %esp
+ call early_all_cores
+
+ movl %ebp, %edi
+ call romstage_main
+ movl %eax, %ebx
- .code64
- call cache_as_ram_main
.code32
#else
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
+ /* Calling conventions preserve BIST in %ebp. */
- /* Restore the cpu_init_detected */
- cvtsd2si %xmm1, %ebx
+ call early_all_cores
+
+ pushl %ebp
+ call romstage_main
+ movl %eax, %ebx
- pushl %ebx /* init detected */
- pushl %edx /* bist */
- call cache_as_ram_main
#endif
- /* Should never see this postcode */
- post_code(0xaf)
-stop:
- jmp stop
+/* Register %ebx is new stacktop for remaining of romstage.
+ * It is the only register preserved in AMD_DISABLE_STACK.
+ */
disable_cache_as_ram:
- /* Save return stack */
- movd 0(%esp), %xmm1
- movd %esp, %xmm0
-
/* Disable cache */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -152,13 +127,20 @@ disable_cache_as_ram:
movl %cr0, %eax
andl $0x9fffffff, %eax
movl %eax, %cr0
- xorl %eax, %eax
- /* Restore the return stack */
wbinvd
- movd %xmm0, %esp
- movd %xmm1, (%esp)
- ret
+
+#ifdef __x86_64__
+.code64
+#endif
+
+ movl %ebx, %esp
+ call romstage_after_car
+
+ /* Should never see this postcode */
+ post_code(0xaf)
+stop:
+ jmp stop
cache_as_ram_setup_out:
#ifdef __x86_64__
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
index 578e178..1a7465d 100644
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -28,6 +28,7 @@
#*****************************************************************************
romstage-y += fixme.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
new file mode 100644
index 0000000..cb325e9
--- /dev/null
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/car.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include "sb_cimx.h"
+#include "SbPlatform.h"
+#include "platform_cfg.h"
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+int platform_once(struct sysinfo *cb)
+{
+ gpioEarlyInit();
+
+ sb_poweron_init();
+
+ return board_BeforeAgesa(cb);
+}
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 9b4e76b..3da8dd5 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c
new file mode 100644
index 0000000..372bd5f
--- /dev/null
+++ b/src/cpu/amd/agesa/family14/romstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/car.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <sb_cimx.h>
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+int platform_once(struct sysinfo *cb)
+{
+ sb_Poweron_Init();
+
+ return board_BeforeAgesa(cb);
+}
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
index 5742e7a..d01cb2a 100644
--- a/src/cpu/amd/agesa/family15/Makefile.inc
+++ b/src/cpu/amd/agesa/family15/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm
romstage-y += fixme.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
new file mode 100644
index 0000000..4b6030d
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/car.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include "northbridge/amd/agesa/family10/reset_test.h"
+#include <nb_cimx.h>
+#include <sb_cimx.h>
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+int platform_once(struct sysinfo *cb)
+{
+ /*
+ * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+ * Disable all Pcie Bridges to work around It.
+ */
+ sr56x0_rd890_disable_pcie_bridge();
+
+ nb_Poweron_Init();
+
+ sb_Poweron_Init();
+
+ return board_BeforeAgesa(cb);
+}
+
+#if 0
+ /* after AMD_INIT_EARLY, before AMD_INIT_POST */
+ nb_Ht_Init();
+
+ /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
+ distinguish_cpu_resets(0);
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
+#endif
diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc
index 98a7050..d4695b0 100644
--- a/src/cpu/amd/agesa/family15rl/Makefile.inc
+++ b/src/cpu/amd/agesa/family15rl/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
new file mode 100644
index 0000000..ae3c37e
--- /dev/null
+++ b/src/cpu/amd/agesa/family15rl/romstage.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/car.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+int platform_once(struct sysinfo *cb)
+{
+ return board_BeforeAgesa(cb);
+}
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 98a7050..d4695b0 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c
new file mode 100644
index 0000000..ae3c37e
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/romstage.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/car.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+int platform_once(struct sysinfo *cb)
+{
+ return board_BeforeAgesa(cb);
+}
diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
index 9367b45..5c2ba8f 100644
--- a/src/cpu/amd/agesa/family16kb/Makefile.inc
+++ b/src/cpu/amd/agesa/family16kb/Makefile.inc
@@ -14,6 +14,7 @@
#
romstage-y += fixme.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c
new file mode 100644
index 0000000..ae3c37e
--- /dev/null
+++ b/src/cpu/amd/agesa/family16kb/romstage.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/car.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+int platform_once(struct sysinfo *cb)
+{
+ return board_BeforeAgesa(cb);
+}
diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
new file mode 100644
index 0000000..f993b2b
--- /dev/null
+++ b/src/cpu/amd/agesa/romstage.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <cbmem.h>
+#include <cpu/amd/car.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/mtrr.h>
+#include <console/console.h>
+#include <halt.h>
+#include <program_loading.h>
+#include <smp/node.h>
+#include <string.h>
+
+#include <Porting.h>
+#include <AMD.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+
+static void init(struct agesa_state *params,
+ struct romstage_params *romstage, AMD_INTERFACE_PARAMS *aip)
+{
+ memset(romstage, 0, sizeof(*romstage));
+
+ memset(aip, 0, sizeof(*aip));
+ aip->StdHeader.CalloutPtr = GetBiosCallout;
+
+ memset(params, 0, sizeof(*params));
+ params->s3resume = acpi_is_wakeup_s3();
+ params->amd_interface_params = aip;
+ params->romstage = romstage;
+ params->apic_id = (u8) (cpuid_ebx(1) >> 24);
+}
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+ struct romstage_params romstage;
+ struct agesa_state params;
+ AMD_INTERFACE_PARAMS aip;
+
+ init(¶ms, &romstage, &aip);
+
+ if ((params.apic_id == 0) && boot_cpu()) {
+
+ platform_once(&romstage);
+
+ console_init();
+ }
+
+ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n",
+ params.apic_id, cpuid_eax(1));
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ agesa_execute_state(¶ms, AMD_INIT_RESET);
+
+ agesa_execute_state(¶ms, AMD_INIT_EARLY);
+
+ if (!params.s3resume)
+ agesa_execute_state(¶ms, AMD_INIT_POST);
+ else
+ agesa_execute_state(¶ms, AMD_INIT_RESUME);
+
+ uintptr_t stack_top = CACHE_TMP_RAMTOP;
+ if (params.s3resume) {
+ if (!cbmem_recovery(1)) {
+ printk(BIOS_EMERG, "Unable to recover CBMEM\n");
+ halt();
+ }
+ stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
+ ROMSTAGE_STACK_CBMEM);
+ stack_top += HIGH_ROMSTAGE_STACK_SIZE;
+ }
+
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ return (void*)stack_top;
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ struct romstage_params romstage;
+ struct agesa_state params;
+ AMD_INTERFACE_PARAMS aip;
+
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+
+ init(¶ms, &romstage, &aip);
+
+ if (!params.s3resume)
+ agesa_execute_state(¶ms, AMD_INIT_ENV);
+ else
+ agesa_execute_state(¶ms, AMD_S3LATE_RESTORE);
+
+ if (params.s3resume)
+ set_resume_cache();
+
+ run_ramstage();
+}
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 1e4aadb..78dec96 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -26,31 +26,7 @@
#include <halt.h>
#include "s3_resume.h"
-static void move_stack_high_mem(void)
-{
- uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
- ROMSTAGE_STACK_CBMEM);
- if (!high_stack)
- halt();
-
- /* TODO: Make the switch with empty stack instead. */
- memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
-
- /* TODO: We only switch stack on BSP. */
-#ifdef __x86_64__
- __asm__
- volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g"
- (high_stack - BSP_STACK_BASE_ADDR)
- :);
-#else
- __asm__
- volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g"
- (high_stack - BSP_STACK_BASE_ADDR)
- :);
-#endif
-}
-
-static void set_resume_cache(void)
+void set_resume_cache(void)
{
msr_t msr;
@@ -74,21 +50,3 @@ static void set_resume_cache(void)
enable_cache();
}
-
-void prepare_for_resume(void)
-{
- if (cbmem_recovery(1)) {
- printk(BIOS_EMERG, "Unable to recover CBMEM\n");
- halt();
- }
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
-}
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index ff23966..a5399c0 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -17,7 +17,7 @@
#define S3_RESUME_H
void restore_mtrr(void);
-void prepare_for_resume(void);
+void set_resume_cache(void);
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
const void *OemS3Saved_MTRR_Storage(void);
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 6950a38..7b7ba45 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -1,6 +1,8 @@
#ifndef _CPU_AMD_CAR_H
#define _CPU_AMD_CAR_H
+#include <arch/cpu.h>
+
void main(unsigned long bist);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
@@ -14,4 +16,32 @@ void cache_as_ram_new_stack(void);
void disable_cache_as_ram(void);
#endif
+struct romstage_params
+{
+ u8 dummy;
+};
+
+struct agesa_state
+{
+ u8 apic_id;
+ u32 func;
+ const char *function_name;
+ u32 status; //AGESA_STATUS
+
+ struct romstage_params *romstage;
+ void *ramstage;
+ void *amd_interface_params;
+
+ u8 s3resume;
+};
+
+void asmlinkage early_all_cores(void);
+void board_BeforeAgesa(struct sysinfo *cb);
+
+void * asmlinkage romstage_main(unsigned long bist);
+void asmlinkage romstage_after_car(void);
+
+int platform_once(struct sysinfo *cb);
+int agesa_execute_state(struct agesa_state *params, int func);
+
#endif
diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c
index 84866de..c2277b1 100644
--- a/src/mainboard/amd/dinar/OemCustomize.c
+++ b/src/mainboard/amd/dinar/OemCustomize.c
@@ -16,6 +16,10 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+}
+
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
@@ -27,7 +31,7 @@
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
// Dinar has the following routing:
// CS0 M[B,A]_CLK_H/L[0]
// CS1 M[B,A]_CLK_H/L[2]
@@ -38,15 +42,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-
-static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost)
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
InitPost->MemConfig.UmaMode = UMA_AUTO;
InitPost->MemConfig.BottomIo = 0xE0;
InitPost->MemConfig.UmaSize = 0xE0-0xC0;
- return AGESA_SUCCESS;
}
-const struct OEM_HOOK OemCustomize = {
- .InitPost = OemInitPost,
-};
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 0edc346..96f5bc4 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -26,33 +26,23 @@
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
+#include "cpu/x86/bist.h"
#include <superio/smsc/sch4037/sch4037.h>
#include <superio/smsc/sio1036/sio1036.h>
-#include <cpu/x86/lapic.h>
+#include "cpu/x86/lapic.h"
#include "nb_cimx.h"
#include <sb_cimx.h>
#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void mainboard_romstage_entry(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+ sch4037_early_init(0x2e);
+ sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+#if 0
if (!cpu_init_detectedx && boot_cpu()) {
-
- post_code(0x30);
-
- sch4037_early_init(0x2e);
-
- sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- post_code(0x31);
- console_init();
-
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
@@ -60,47 +50,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sr56x0_rd890_disable_pcie_bridge();
}
-
- /* Halt if there was a built in self test failure */
- post_code(0x33);
- report_bist_failure(bist);
-
- // Load MPB
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- if(boot_cpu()) {
- post_code(0x34);
- sb_Poweron_Init();
- }
-
- post_code(0x35);
- agesawrapper_amdinitreset();
-
- post_code(0x36);
- agesawrapper_amdinitearly();
-
- post_code(0x37);
- nb_Poweron_Init();
- post_code(0x38);
- nb_Ht_Init();
-
-
- post_code(0x39);
- agesawrapper_amdinitpost();
-
- post_code(0x40);
- agesawrapper_amdinitenv();
-
-
- post_code(0x43);
- printk(BIOS_DEBUG, "Disabling cache as RAM ");
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "done\n");
-
- post_code(0x44);
- copy_and_run();
-
- post_code(0x45); // Should never see this post code.
-}
+#endif
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
index d1f715c..e304064 100644
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -38,7 +38,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -126,7 +126,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -140,12 +139,17 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 3d0eecf..71767a5 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -13,71 +13,13 @@
* GNU General Public License for more details.
*/
-#include <lib.h>
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/smsc/kbc1100/kbc1100.h>
-#include <cpu/x86/lapic.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- kbc1100_early_init(0x2e);
- kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+ kbc1100_early_init(0x2e);
+ kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c
index 70c5035..0969d82 100644
--- a/src/mainboard/amd/olivehill/OemCustomize.c
+++ b/src/mainboard/amd/olivehill/OemCustomize.c
@@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define SEED_A 0x12
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
@@ -182,7 +174,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c
index 61272d0..0881591 100644
--- a/src/mainboard/amd/olivehill/mainboard.c
+++ b/src/mainboard/amd/olivehill/mainboard.c
@@ -31,9 +31,6 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index bb1ad30..9bad0b5 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -17,29 +17,22 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include "cbmem.h"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
+ /* For serial port option, plug-in card on LPC. */
+ device_t dev = PCI_DEV(0, 0x14, 3);
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+ hudson_lpc_port80();
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
@@ -49,67 +42,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- /* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
+}
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+#if 0
+ /* LPC clock? Should happen before enable_serial. */
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for(i = 0; i < 200000; i++)
val = inb(0xcd6);
+#endif
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
+#if 0
+ /* Was before copy_and_run. */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c
index fb6177a..7fc900f 100644
--- a/src/mainboard/amd/parmer/OemCustomize.c
+++ b/src/mainboard/amd/parmer/OemCustomize.c
@@ -157,7 +157,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -189,14 +189,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
@@ -221,7 +213,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
index c519772..1626355 100644
--- a/src/mainboard/amd/parmer/mainboard.c
+++ b/src/mainboard/amd/parmer/mainboard.c
@@ -31,9 +31,6 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 1f251ab..1a65d8a 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -33,63 +33,12 @@
#include <cpu/amd/agesa/s3_resume.h>
#include "cbmem.h"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
-
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- post_code(0x54); /* Should never see this post code. */
+ /* For serial port option, plug-in card on LPC. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
}
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
index 825364e..5cdc27c 100644
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ b/src/mainboard/amd/persimmon/OemCustomize.c
@@ -36,7 +36,7 @@
*
**/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -146,12 +145,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index c8a8d74..113e256 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -13,90 +13,13 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include "cbmem.h"
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x42);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
index 74b0aa8..55f9e81 100644
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ b/src/mainboard/amd/south_station/OemCustomize.c
@@ -38,7 +38,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -134,7 +134,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -148,12 +147,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 95f6dde..113e256 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -13,71 +13,13 @@
* GNU General Public License for more details.
*/
-#include <lib.h>
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h>
-#include <cpu/x86/lapic.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c
index 66058f2..c94c722 100644
--- a/src/mainboard/amd/thatcher/OemCustomize.c
+++ b/src/mainboard/amd/thatcher/OemCustomize.c
@@ -163,7 +163,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr;
@@ -215,14 +215,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -236,7 +228,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
@@ -247,7 +239,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
index c89ce5a..c929bb2 100644
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ b/src/mainboard/amd/thatcher/mainboard.c
@@ -46,9 +46,6 @@ static void mainboard_enable(device_t dev)
msr = rdmsr(0xC0011023);
msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr);
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 147f31a..3e149b7 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -22,88 +22,43 @@
#include <arch/stages.h>
#include <device/pnp_def.h>
#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
+
+#include <cpu/amd/car.h>
#include <superio/smsc/lpc47n217/lpc47n217.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include "cbmem.h"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
u8 byte;
pci_devfn_t dev;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
/* Set LPC decode enables. */
dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
-
hudson_lpc_port80();
+
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
- *(u8 *)0xfed80101 = 0x98;
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
+ post_code(0x30);
+ /* For serial port. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
- post_code(0x50);
- copy_and_run();
+ post_code(0x31);
+ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- post_code(0x54); /* Should never see this post code. */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+ outb(0xea, 0xcd6);
+ outb(0x1, 0xcd7);
+ *(u8 *)0xfed80101 = 0x98;
}
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 3c20047..43af09f 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -105,7 +105,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *LlanoPcieComplexListPtr;
@@ -159,7 +159,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -173,12 +172,17 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index d28608e..71767a5 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -13,81 +13,13 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/smsc/kbc1100/kbc1100.h>
-#include <cpu/x86/lapic.h>
-#include "sb_cimx.h"
-#include "SbPlatform.h"
-#include <arch/cpu.h>
-#include "platform_cfg.h"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- post_code(0x35);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- gpioEarlyInit();
- sb_poweron_init();
-
- post_code(0x31);
-
- kbc1100_early_init(0x2e);
- kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- post_code(0x32);
- post_code(0x33);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- // Load MPB
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x36);
- agesawrapper_amdinitreset();
-
- post_code(0x37);
- agesawrapper_amdinitearly();
-
- post_code(0x38);
- agesawrapper_amdinitpost();
-
- post_code(0x39);
- printk(BIOS_DEBUG, "sb_before_pci_init ");
- sb_before_pci_init();
- printk(BIOS_DEBUG, "passed.\n");
-
- post_code(0x40);
- agesawrapper_amdinitenv();
-
- post_code(0x43);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run returned!\n");
-
- post_code(0x44); // Should never see this post code.
+ kbc1100_early_init(0x2e);
+ kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 6f4dbfc..c1eb801 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -42,7 +42,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -140,7 +140,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -154,12 +153,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 7a5d348..40ada8e 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -13,68 +13,6 @@
* GNU General Public License for more details.
*/
-#include <lib.h>
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c
index ab563ae..99aca7f 100644
--- a/src/mainboard/asrock/e350m1/OemCustomize.c
+++ b/src/mainboard/asrock/e350m1/OemCustomize.c
@@ -42,7 +42,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -120,7 +120,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -134,12 +133,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 82fbecf..6bba343 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -13,87 +13,15 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5572d/nct5572d.h>
-#include <cpu/x86/lapic.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x42);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ return 0;
}
diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c
index aec1343..a923e78 100644
--- a/src/mainboard/asrock/imb-a180/OemCustomize.c
+++ b/src/mainboard/asrock/imb-a180/OemCustomize.c
@@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define SEED_A 0x12
HW_RXEN_SEED(
@@ -183,7 +175,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
+
diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c
index 61272d0..0881591 100644
--- a/src/mainboard/asrock/imb-a180/mainboard.c
+++ b/src/mainboard/asrock/imb-a180/mainboard.c
@@ -31,9 +31,6 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 29d831d..e9d7895 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -21,44 +21,25 @@
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include "cbmem.h"
+
+#include <cpu/amd/car.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627uhg/w83627uhg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val, t32;
- u32 *addr32;
-
- /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
- * even though the register is not documented in the Kabini BKDG.
- * Otherwise the serial output is bad code.
- */
- //outb(0xD2, 0xcd6);
- //outb(0x00, 0xcd7);
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80();
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
@@ -76,64 +57,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
t32 &= 0xffffbffb;
*addr32 = t32;
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- post_code(0x31);
-
- /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ device_t dev = PCI_DEV(0, 0x14, 3);
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
- console_init();
- }
+ /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ return 0;
+}
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+#if 0
+ /* LPC clock? Should happen before enable_serial. */
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for(i = 0; i < 200000; i++)
val = inb(0xcd6);
+#endif
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
+#if 0
+ /* Was before copy_and_run. */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
+#endif
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 6348d5a..29d3f7a 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -139,7 +139,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr;
@@ -190,14 +190,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -212,7 +204,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
@@ -227,7 +219,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
};
#endif /* CONFIG_BOARD_ASUS_F2A85_M */
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
+
diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c
index 2566037..6e6d193 100644
--- a/src/mainboard/asus/f2a85-m/mainboard.c
+++ b/src/mainboard/asus/f2a85-m/mainboard.c
@@ -46,9 +46,6 @@ static void mainboard_enable(device_t dev)
msr = rdmsr(0xC0011023);
msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr);
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 51cadc7..910863a 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -14,29 +14,20 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#include <arch/acpi.h>
-#include <arch/cpu.h>
#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
#include <console/console.h>
-#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_def.h>
+#include <stdint.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
-#include <stdint.h>
-#include <string.h>
+
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
+
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
@@ -58,97 +49,52 @@ static void sbxxx_enable_48mhzout(void)
SB_MMIO_MISC32(0x40) = reg32;
}
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
u8 byte;
pci_devfn_t dev;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
-#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
- hudson_pci_port80();
-#endif
-#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
- hudson_lpc_port80();
-#endif
-
- if (!cpu_init_detectedx && boot_cpu()) {
-
- /* enable SIO LPC decode */
- dev = PCI_DEV(0, 0x14, 3);
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
-
- /* enable serial decode */
- byte = pci_read_config8(dev, 0x44);
- byte |= (1 << 6); /* 0x3f8 */
- pci_write_config8(dev, 0x44, byte);
-
- post_code(0x30);
-
- /* enable SB MMIO space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
-
- /* enable SIO clock */
- sbxxx_enable_48mhzout();
- ite_kill_watchdog(GPIO_DEV);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_enable_3vsbsw(GPIO_DEV);
- console_init();
-
- /* turn on secondary smbus at b20 */
- outb(0x28, 0xcd6);
- byte = inb(0xcd7);
- byte |= 1;
- outb(byte, 0xcd7);
-
- /* set DDR3 voltage */
- byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
-
- /* default is byte = 0x0, so no need to set it in this case */
- if (byte)
- do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+ ite_kill_watchdog(GPIO_DEV);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(GPIO_DEV);
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+
+ return 0;
}
diff --git a/src/mainboard/asus/f2a85-m_le/OemCustomize.c b/src/mainboard/asus/f2a85-m_le/OemCustomize.c
index ea1c871..4ec6f5a 100644
--- a/src/mainboard/asus/f2a85-m_le/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m_le/OemCustomize.c
@@ -11,7 +11,7 @@
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c
index 752293a..31bf59f 100644
--- a/src/mainboard/bap/ode_e20XX/OemCustomize.c
+++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c
@@ -105,7 +105,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -127,14 +127,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -148,7 +140,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define SEED_WL 0x0E
WRITE_LEVELING_SEED(
@@ -174,7 +166,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c
index baddf0b..16fda90 100644
--- a/src/mainboard/bap/ode_e20XX/mainboard.c
+++ b/src/mainboard/bap/ode_e20XX/mainboard.c
@@ -121,9 +121,6 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index a43d035..78007fd 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -15,36 +15,21 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
+
+#include <cpu/amd/car.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81866d/f81866d.h>
-#include "cbmem.h"
+
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
+ fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
+}
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+#if 0
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -52,62 +37,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for(i = 0; i < 200000; i++)
val = inb(0xcd6);
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c
index c44a994..92e09f0 100644
--- a/src/mainboard/biostar/am1ml/OemCustomize.c
+++ b/src/mainboard/biostar/am1ml/OemCustomize.c
@@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define SEED_A 0x12
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
@@ -182,7 +174,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c
index 7dc9f4d..75a52e0 100644
--- a/src/mainboard/biostar/am1ml/mainboard.c
+++ b/src/mainboard/biostar/am1ml/mainboard.c
@@ -112,9 +112,6 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index 1672349..46c6456 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -14,26 +14,15 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
-#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
+
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include "cbmem.h"
+
+#include <cpu/amd/car.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
@@ -105,17 +94,18 @@ static void ite_gpio_conf(pnp_devfn_t dev)
ite_exit_conf (dev);
}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
+ ite_kill_watchdog(GPIO_DEV);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+#if 0
u32 val, t32;
u8 byte;
pci_devfn_t dev;
u32 *addr32;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
* even though the register is not documented in the Kabini BKDG.
@@ -146,83 +136,36 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
t32 &= 0xffffbffb;
*addr32 = t32;
- if (!cpu_init_detectedx && boot_cpu()) {
- /* enable SIO LPC decode */
- dev = PCI_DEV(0, 0x14, 3);
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
-
- /* enable serial decode */
- byte = pci_read_config8(dev, 0x44);
- byte |= (1 << 6); /* 0x3f8 */
- pci_write_config8(dev, 0x44, byte);
- post_code(0x30);
- post_code(0x31);
-
- /* run ite */
- ite_kill_watchdog(GPIO_DEV);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
- }
- printk(BIOS_DEBUG, "Console inited!\n");
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+#endif
+
+#if 0
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for(i = 0; i < 200000; i++)
val = inb(0xcd6);
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
post_code(0x50);
+
/* This functions configure SIO as it been done under vendor bios */
printk(BIOS_DEBUG, "ITE CONFIG ENVC\n");
ite_evc_conf(ENVC_DEV);
printk(BIOS_DEBUG, "ITE CONFIG GPIO\n");
ite_gpio_conf(GPIO_DEV);
printk(BIOS_DEBUG, "ITE CONFIG DONE\n");
-
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c
index 825364e..8f8b462 100644
--- a/src/mainboard/elmex/pcm205400/OemCustomize.c
+++ b/src/mainboard/elmex/pcm205400/OemCustomize.c
@@ -36,7 +36,7 @@
*
**/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -146,12 +145,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p)
+{
+}
diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c
index c8a8d74..e6515e9 100644
--- a/src/mainboard/elmex/pcm205400/romstage.c
+++ b/src/mainboard/elmex/pcm205400/romstage.c
@@ -13,90 +13,14 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include "cbmem.h"
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x42);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ return 0;
}
diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
index 2184fb2..66e30ad 100644
--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
@@ -41,7 +41,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -137,7 +137,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -151,7 +150,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
@@ -168,6 +167,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p)
+{
+}
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 6d06621..19a9254 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -14,84 +14,9 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/cache.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include "cbmem.h"
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/agesa/s3_resume.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
-
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x42);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+ return 0;
}
diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
index 933b036..23c2485 100644
--- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
@@ -114,7 +114,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -136,14 +136,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -157,7 +149,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define SEED_WL 0x0E
WRITE_LEVELING_SEED(
@@ -183,7 +175,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c
index baddf0b..f0cca4e 100644
--- a/src/mainboard/gizmosphere/gizmo2/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c
@@ -120,10 +120,6 @@ static void pirq_setup(void)
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index bb1ad30..40d7add 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -17,29 +17,22 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <commonlib/loglevel.h>
+#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include "cbmem.h"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
+ /* For serial port option, plug-in card on LPC. */
+ device_t dev = PCI_DEV(0, 0x14, 3);
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+ hudson_lpc_port80();
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
@@ -49,67 +42,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- /* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
+}
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+#if 0
+ /* LPC clock? Should happen before enable_serial. */
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for(i = 0; i < 200000; i++)
val = inb(0xcd6);
+#endif
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
+#if 0
+ /* Was before copy_and_run. */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c
index 730c97e..193961e 100644
--- a/src/mainboard/hp/abm/OemCustomize.c
+++ b/src/mainboard/hp/abm/OemCustomize.c
@@ -116,7 +116,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -138,14 +138,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -159,7 +151,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define SEED_A 0x12
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
@@ -178,7 +170,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c
index 45e2f81..451d9e9 100644
--- a/src/mainboard/hp/abm/mainboard.c
+++ b/src/mainboard/hp/abm/mainboard.c
@@ -114,9 +114,6 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 02ebbc9..23e5d4c 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -25,7 +25,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <commonlib/loglevel.h>
+#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
@@ -33,26 +33,30 @@
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cbmem.h>
+
+#include <cpu/amd/car.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val, t32;
- u32 *addr32;
-
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /* Set LPC decode enables. */
+ /* For serial port option, plug-in card on LPC. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
+ /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
+ * even though the register is not documented in the Kabini BKDG.
+ * Otherwise the serial output is bad code.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
outb(0x01, 0xcd7);
@@ -71,58 +75,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
t32 &= 0xffffff7b; // clear 2, 7
*addr32 = t32;
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- post_code(0x31);
-
- nct5104d_enable_uartd(SERIAL_DEV);
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
+ nct5104d_enable_uartd(SERIAL_DEV);
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
+}
- post_code(0x61);
- prepare_for_resume();
- }
+#if 0
+ /* Was before copy_and_run. */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
index 605c7d3..1f1ec2f 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
@@ -156,7 +156,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -188,14 +188,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* If PlatformSpecificTable is populated, AGESA will base its settings on the
* data from the table. Otherwise, it will use its default conservative settings
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
@@ -222,7 +214,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
index d20bc87..ba2b2e6 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
@@ -44,11 +44,8 @@ static void mainboard_enable(device_t dev)
hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
hudson_enable_smi_generation();
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
- else
+ if (!acpi_is_wakeup_s3())
pavilion_cold_boot_init();
-
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 714743b..24ec37a 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -13,76 +13,10 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#include <arch/acpi.h>
-#include <arch/cpu.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/car.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+void board_BeforeAgesa(struct sysinfo *cb)
+{
hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
index f980a15..626215d 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
@@ -35,7 +35,7 @@
*
**/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
void *BrazosPcieComplexListPtr;
@@ -176,7 +176,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/**
@@ -188,12 +187,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* If PlatformSpecificTable is populated, AGESA will base its settings on the
* data from the table. Otherwise, it will use its default conservative settings.
*/
-const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p)
+{
+}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 85a4343..239bfed 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -14,105 +14,14 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#include <arch/acpi.h>
-#include <arch/cpu.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
-
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/mtrr.h>
#include <cpu/amd/car.h>
-#include <sb_cimx.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
-/*
- * Possible AGESA_STATUS values:
- *
- * 0x0 = AGESA_SUCCESS
- * 0x1 = AGESA_UNSUPPORTED
- * 0x2 = AGESA_BOUNDS_CHK
- * 0x3 = AGESA_ALERT
- * 0x4 = AGESA_WARNING
- * 0x5 = AGESA_ERROR
- * 0x6 = AGESA_CRITICAL
- * 0x7 = AGESA_FATAL
- */
-
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x42);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
index 605c7d3..1f1ec2f 100644
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ b/src/mainboard/lenovo/g505s/OemCustomize.c
@@ -156,7 +156,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -188,14 +188,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* If PlatformSpecificTable is populated, AGESA will base its settings on the
* data from the table. Otherwise, it will use its default conservative settings
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
@@ -222,7 +214,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
index bcc3cf2..cca2807 100644
--- a/src/mainboard/lenovo/g505s/mainboard.c
+++ b/src/mainboard/lenovo/g505s/mainboard.c
@@ -44,9 +44,7 @@ static void mainboard_enable(device_t dev)
hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
hudson_enable_smi_generation();
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
- else
+ if (!acpi_is_wakeup_s3())
pavilion_cold_boot_init();
}
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index 714743b..2bb534c 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -13,76 +13,11 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#include <arch/acpi.h>
-#include <arch/cpu.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <cpu/amd/car.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
+ return 0;
}
diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
index 63466b9..e18c911 100644
--- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c
+++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
@@ -42,7 +42,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -152,13 +151,18 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p)
+{
+}
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 37dc37f..d87c11f 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -13,67 +13,17 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include "cbmem.h"
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
+ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
+#if 0
post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
* hang, looks like DRAM re-init goes wrong, don't know why. */
@@ -83,23 +33,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c
index a5f4921..e7ee3d3 100644
--- a/src/mainboard/lippert/toucan-af/OemCustomize.c
+++ b/src/mainboard/lippert/toucan-af/OemCustomize.c
@@ -42,7 +42,7 @@
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -152,13 +151,18 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p)
+{
+}
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index adc2987..fb4619a 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -13,68 +13,19 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include "cbmem.h"
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/agesa/s3_resume.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
-
- post_code(0x31);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
+#if 0
post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
* hang, looks like DRAM re-init goes wrong, don't know why. */
@@ -84,23 +35,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
-}
+#endif
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index 90bc5a9..10edcf3 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -146,7 +146,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
**/
/*---------------------------------------------------------------------------------------*/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr;
@@ -197,14 +197,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
- /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
- InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -218,7 +210,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
@@ -232,7 +224,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
- .InitMid = OemInitMid,
-};
+
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c
index 2566037..6e6d193 100644
--- a/src/mainboard/msi/ms7721/mainboard.c
+++ b/src/mainboard/msi/ms7721/mainboard.c
@@ -46,9 +46,6 @@ static void mainboard_enable(device_t dev)
msr = rdmsr(0xC0011023);
msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr);
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 9ce47f2..db70053 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -15,30 +15,19 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#include <arch/acpi.h>
-#include <arch/cpu.h>
#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
#include <console/console.h>
-#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_def.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include <northbridge/amd/agesa/agesawrapper.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <southbridge/amd/agesa/hudson/smbus.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h>
-#include <stdint.h>
-#include <string.h>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
@@ -122,91 +111,41 @@ static void sbxxx_enable_48mhzout(void)
SB_MMIO_MISC32(0x40) = reg32;
}
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
u8 byte;
pci_devfn_t dev;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
-#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
- hudson_pci_port80();
-#endif
-#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
- hudson_lpc_port80();
-#endif
-
- if (!cpu_init_detectedx && boot_cpu()) {
-
- /* enable SIO LPC decode */
- dev = PCI_DEV(0, 0x14, 3);
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
-
- /* enable serial decode */
- byte = pci_read_config8(dev, 0x44);
- byte |= (1 << 6); /* 0x3f8 */
- pci_write_config8(dev, 0x44, byte);
-
- post_code(0x30);
-
- /* enable SB MMIO space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
-
- /* enable SIO clock */
- sbxxx_enable_48mhzout();
-
- /* Initialize GPIO registers */
- gpio_init(GPIO_DEV);
-
- /* Enable serial console */
- fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* turn on secondary smbus at b20 */
- outb(0x28, 0xcd6);
- byte = inb(0xcd7);
- byte |= 1;
- outb(byte, 0xcd7);
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
- post_code(0x60);
- agesawrapper_amdinitresume();
- amd_initcpuio();
- agesawrapper_amds3laterestore();
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ /* Initialize GPIO registers */
+ gpio_init(GPIO_DEV);
+
+ /* Enable serial console */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ return 0;
}
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index 20acb27..213ecdf 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -35,7 +35,7 @@
*
**/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -124,7 +124,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -138,7 +137,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
@@ -155,6 +154,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p)
+{
+}
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index a74d247..ac88931 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -15,99 +15,16 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <southbridge/amd/cimx/cimx_util.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/cache.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
-#include "cbmem.h"
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/agesa/s3_resume.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
#include "gpio_ftns.h"
+#include "SB800.h"
#define SIO_PORT 0x2e
#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
-static void early_lpc_init(void);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_Poweron_Init();
- early_lpc_init();
-
-
- post_code(0x31);
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x42);
- agesawrapper_amdinitenv();
- amd_initenv();
-
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
- printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
- post_code(0x54); /* Should never see this post code. */
-}
-
static void early_lpc_init(void)
{
u32 mmio_base;
@@ -140,3 +57,10 @@ static void early_lpc_init(void)
configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ early_lpc_init();
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ return 0;
+}
diff --git a/src/mainboard/supermicro/h8qgi/OemCustomize.c b/src/mainboard/supermicro/h8qgi/OemCustomize.c
index 9f340c6..2bdb3c7 100644
--- a/src/mainboard/supermicro/h8qgi/OemCustomize.c
+++ b/src/mainboard/supermicro/h8qgi/OemCustomize.c
@@ -16,6 +16,10 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+}
+
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
@@ -37,7 +41,7 @@
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
WRITE_LEVELING_SEED(
ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
@@ -65,5 +69,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 19ffbdf..ffa4045 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -20,11 +20,11 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <arch/stages.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic.h"
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/family10/reset_test.h>
+#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
#include <superio/nuvoton/wpcm450/wpcm450.h>
@@ -36,34 +36,15 @@
*/
#define SIO_PORT 0x164e
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void mainboard_romstage_entry(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- post_code(0x31);
-
- /* Halt if there was a built in self test failure */
- post_code(0x33);
- report_bist_failure(bist);
-
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
- post_code(0x34);
- post_code(0x35);
- console_init();
-
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
+}
+#if 0
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
@@ -76,16 +57,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
sb_Poweron_Init();
}
- post_code(0x3B);
- agesawrapper_amdinitearly();
+#endif
- post_code(0x3C);
+#if 0
/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
* In order to access W83795G/ADG HWM using I2C protocol,
* we select function to SDA, SCL function (or GP33, GP32 function).
*/
w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
+#endif
+#if 0
nb_Ht_Init();
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
@@ -95,23 +77,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- post_code(0x42);
-
- post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as RAM ");
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "done\n");
-
- post_code(0x51);
- copy_and_run();
-
- /* We will not return, Should never see this message and post code. */
- printk(BIOS_DEBUG, "should not be here -\n");
- post_code(0x54);
-}
+#endif
diff --git a/src/mainboard/supermicro/h8scm/OemCustomize.c b/src/mainboard/supermicro/h8scm/OemCustomize.c
index 634d06b..ff82dba 100644
--- a/src/mainboard/supermicro/h8scm/OemCustomize.c
+++ b/src/mainboard/supermicro/h8scm/OemCustomize.c
@@ -16,6 +16,10 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+}
+
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
@@ -35,10 +39,10 @@
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
- * I am not sure whether DefaultPlatformMemoryConfiguration is necessary.
+ * I am not sure whether PlatformMemoryTable is necessary.
* If I comment out these code, H8SCM will still pass mem training.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
WRITE_LEVELING_SEED(
ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
@@ -66,5 +70,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 918d9ad..6619b2e 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -20,49 +20,31 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <arch/stages.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic.h"
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/family10/reset_test.h>
+#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
#include <superio/nuvoton/wpcm450/wpcm450.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
+/* though UARTs are on the NUVOTON BMC, port 0x164E
+ * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+ */
+#define SIO_PORT 0x164e
-#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void mainboard_romstage_entry(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- post_code(0x31);
-
- /* Halt if there was a built in self test failure */
- post_code(0x33);
- report_bist_failure(bist);
-
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
- wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
+ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
- post_code(0x34);
-
- post_code(0x35);
- console_init();
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
+}
+#if 0
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
@@ -75,37 +57,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
sb_Poweron_Init();
}
- post_code(0x3B);
- agesawrapper_amdinitearly();
-
- post_code(0x3C);
- nb_Ht_Init();
-
- post_code(0x3D);
- /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- distinguish_cpu_resets(0);
- soft_reset();
- die("After soft_reset_x - shouldn't see this message!!!\n");
- }
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- post_code(0x42);
-
- post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as RAM ");
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "done\n");
-
- post_code(0x51);
- copy_and_run();
-
- /* We will not return, Should never see this message and post code. */
- printk(BIOS_DEBUG, "should not be here -\n");
- post_code(0x54);
-}
+#endif
diff --git a/src/mainboard/tyan/s8226/OemCustomize.c b/src/mainboard/tyan/s8226/OemCustomize.c
index d3a8f4b..baa77c5 100644
--- a/src/mainboard/tyan/s8226/OemCustomize.c
+++ b/src/mainboard/tyan/s8226/OemCustomize.c
@@ -16,6 +16,10 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+}
+
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
@@ -37,7 +41,7 @@
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
WRITE_LEVELING_SEED(
ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
@@ -66,5 +70,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
-};
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *InitMid)
+{
+}
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index d43c04b..0657cf6 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -20,11 +20,11 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <arch/stages.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic.h"
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/family10/reset_test.h>
+#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
#include <superio/winbond/common/winbond.h>
@@ -34,39 +34,21 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void mainboard_romstage_entry(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- post_code(0x31);
-
/* For serial port. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
- /* Halt if there was a built in self test failure */
- post_code(0x33);
- report_bist_failure(bist);
-
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
w83627dhg_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
- post_code(0x34);
-
- post_code(0x35);
- console_init();
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x37);
- agesawrapper_amdinitreset();
+}
+#if 0
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
@@ -79,16 +61,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
sb_Poweron_Init();
}
- post_code(0x3B);
- agesawrapper_amdinitearly();
+#endif
- post_code(0x3C);
+#if 0
/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
* In order to access W83795G/ADG HWM using I2C protocol,
* we select function to SDA, SCL function (or GP33, GP32 function).
*/
w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
+#endif
+#if 0
nb_Ht_Init();
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
@@ -99,22 +82,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
die("After soft_reset_x - shouldn't see this message!!!\n");
}
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- post_code(0x42);
-
- post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as RAM ");
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "done\n");
-
- post_code(0x51);
- copy_and_run();
-
- /* We will not return, Should never see this message and post code. */
- printk(BIOS_DEBUG, "should not be here -\n");
- post_code(0x54);
-}
+#endif
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 62a5df1..1d153ac 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -23,8 +23,11 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
-romstage-y += def_callouts.c agesawrapper.c eventlog.c
-ramstage-y += def_callouts.c agesawrapper.c eventlog.c
+romstage-y += def_callouts.c eventlog.c
+ramstage-y += def_callouts.c eventlog.c
+
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
romstage-y += oem_s3.c
ramstage-y += oem_s3.c
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c
deleted file mode 100644
index a72e239..0000000
--- a/src/northbridge/amd/agesa/agesawrapper.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
-#include "heapManager.h"
-
-static const struct OEM_HOOK *OemHook = &OemCustomize;
-
-#if defined(__PRE_RAM__)
-
-AGESA_STATUS agesawrapper_amdinitreset(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_RESET_PARAMS AmdResetParams;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
- memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
- AmdParamStruct.AllocationMethod = ByHost;
- AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
- AmdParamStruct.NewStructPtr = &AmdResetParams;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
- AmdCreateStruct(&AmdParamStruct);
- AmdResetParams.HtConfig.Depth = 0;
-
- status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
- AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
- AmdReleaseStruct(&AmdParamStruct);
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitearly(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
- AmdParamStruct.AllocationMethod = PreMemHeap;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
- AmdCreateStruct(&AmdParamStruct);
-
- /* OEM Should Customize the defaults through this hook. */
- AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
- if (OemHook->InitEarly)
- OemHook->InitEarly(AmdEarlyParamsPtr);
-
- status = AmdInitEarly(AmdEarlyParamsPtr);
- AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
-
- AmdReleaseStruct(&AmdParamStruct);
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitpost(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_POST_PARAMS *PostParams;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
- AmdParamStruct.AllocationMethod = PreMemHeap;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
- AmdCreateStruct(&AmdParamStruct);
-
- /* OEM Should Customize the defaults through this hook. */
- PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
- if (OemHook->InitPost)
- OemHook->InitPost(PostParams);
-
- status = AmdInitPost(PostParams);
- AGESA_EVENTLOG(status, &PostParams->StdHeader);
-
- AmdReleaseStruct(&AmdParamStruct);
-
- /* Initialize heap space */
- EmptyHeap();
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitresume(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_RESUME_PARAMS *AmdResumeParamsPtr;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
- AmdParamStruct.AllocationMethod = PreMemHeap;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
- AmdCreateStruct(&AmdParamStruct);
-
- AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
-
- AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
- AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
- OemInitResume(AmdResumeParamsPtr);
-
- status = AmdInitResume(AmdResumeParamsPtr);
-
- AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
- AmdReleaseStruct(&AmdParamStruct);
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitenv(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_ENV_PARAMS *EnvParam;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
- AmdParamStruct.AllocationMethod = PostMemDram;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
- AmdCreateStruct(&AmdParamStruct);
- EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
-
- status = AmdInitEnv(EnvParam);
- AGESA_EVENTLOG(status, &EnvParam->StdHeader);
-
- AmdReleaseStruct(&AmdParamStruct);
- return status;
-}
-
-AGESA_STATUS agesawrapper_amds3laterestore(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdInterfaceParams;
- AMD_S3LATE_PARAMS AmdS3LateParams;
- AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
-
- memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
-
- AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
- AmdInterfaceParams.AllocationMethod = ByHost;
- AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
- AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
- AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdS3LateParamsPtr = &AmdS3LateParams;
- AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
-
- AmdCreateStruct(&AmdInterfaceParams);
-
-#if 0
- /* TODO: What to do with NvStorage here? */
- AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0;
-#endif
- AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
- OemS3LateRestore(AmdS3LateParamsPtr);
-
- status = AmdS3LateRestore(AmdS3LateParamsPtr);
- AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- return status;
-}
-
-#else /* __PRE_RAM__ */
-
-AGESA_STATUS agesawrapper_amdinitmid(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_MID_PARAMS *MidParam;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
- AmdParamStruct.AllocationMethod = PostMemDram;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
- AmdCreateStruct(&AmdParamStruct);
-
- /* OEM Should Customize the defaults through this hook. */
- MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr;
- if (OemHook->InitMid)
- OemHook->InitMid(MidParam);
-
- status = AmdInitMid(MidParam);
- AGESA_EVENTLOG(status, &MidParam->StdHeader);
- AmdReleaseStruct(&AmdParamStruct);
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdS3Save(void)
-{
- AGESA_STATUS status;
- AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
- AMD_INTERFACE_PARAMS AmdInterfaceParams;
-
- memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
- AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdInterfaceParams.AllocationMethod = PostMemDram;
- AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
- AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
- AmdInterfaceParams.StdHeader.Func = 0;
- AmdCreateStruct(&AmdInterfaceParams);
-
- AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
- AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
-
- status = AmdS3Save(AmdS3SaveParamsPtr);
- AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- OemS3Save(AmdS3SaveParamsPtr);
-
- AmdReleaseStruct(&AmdInterfaceParams);
-
- return status;
-}
-
-/* We will reference AmdLateParams later to copy ACPI tables. */
-static AMD_LATE_PARAMS *AmdLateParams = NULL;
-
-AGESA_STATUS agesawrapper_amdinitlate(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
- AmdParamStruct.AllocationMethod = PostMemDram;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \
- IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)
- AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-#endif
-
- AmdCreateStruct(&AmdParamStruct);
- AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
- status = AmdInitLate(AmdLateParams);
- AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */
- return status;
-}
-
-void *agesawrapper_getlateinitptr(int pick)
-{
- ASSERT(AmdLateParams != NULL);
-
- switch (pick) {
- case PICK_DMI:
- return AmdLateParams->DmiTable;
- case PICK_PSTATE:
- return AmdLateParams->AcpiPState;
- case PICK_SRAT:
- return AmdLateParams->AcpiSrat;
- case PICK_SLIT:
- return AmdLateParams->AcpiSlit;
- case PICK_WHEA_MCE:
- return AmdLateParams->AcpiWheaMce;
- case PICK_WHEA_CMC:
- return AmdLateParams->AcpiWheaCmc;
- case PICK_ALIB:
- return AmdLateParams->AcpiAlib;
- case PICK_IVRS:
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14)
- return NULL;
-#else
- return AmdLateParams->AcpiIvrs;
-#endif
- default:
- return NULL;
- }
- return NULL;
-}
-
-#endif /* __PRE_RAM__ */
-
-AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
-{
- AGESA_STATUS status;
- AP_EXE_PARAMS ApExeParams;
-
- memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
-
- ApExeParams.StdHeader.AltImageBasePtr = 0;
- ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout;
- ApExeParams.StdHeader.Func = 0;
- ApExeParams.StdHeader.ImageBasePtr = 0;
- ApExeParams.FunctionNumber = Func;
- ApExeParams.RelatedDataBlock = ConfigPtr;
-
- status = AmdLateRunApTask(&ApExeParams);
- AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- return status;
-}
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index f5d52d6..6d1d775 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -38,6 +38,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void);
AGESA_STATUS agesawrapper_amdinitpost(void);
AGESA_STATUS agesawrapper_amdinitmid(void);
+const char *agesa_struct_name(int state);
+const char *heap_status_name(int status);
void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func);
#define AGESA_EVENTLOG(status, stdheader) \
agesawrapper_trace(status, stdheader, __func__)
@@ -68,8 +70,27 @@ struct OEM_HOOK
extern const struct OEM_HOOK OemCustomize;
/* For suspend-to-ram support. */
-AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams);
-AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams);
-AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams);
+AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *Resume);
+AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3Late);
+AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3Save);
+
+struct romstage_params;
+void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early);
+void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post);
+void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid);
+
+void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset);
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early);
+void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post);
+void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post);
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env);
+void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env);
+void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid);
+void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late);
+
+void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume);
+void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late);
+void platform_AfterS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late);
+void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save);
#endif /* _AGESAWRAPPER_H_ */
diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c
index 0a40672..590c194 100644
--- a/src/northbridge/amd/agesa/eventlog.c
+++ b/src/northbridge/amd/agesa/eventlog.c
@@ -21,6 +21,40 @@
#include "AGESA.h"
#include "AMD.h"
+#include <heapManager.h>
+
+static const char undefined[] = "undefined";
+
+/* Match order of enum AGESA_STRUCT_NAME. */
+static const char *AgesaFunctionNameStr[] = {
+ "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate",
+ "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct",
+ "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore",
+ "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm",
+};
+
+/* heapManager.h */
+static const char *HeapStatusStr[] = {
+ "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume"
+};
+
+const char *agesa_struct_name(int state)
+{
+ if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS))
+ return undefined;
+
+ int index = state - AMD_INIT_RECOVERY;
+ return AgesaFunctionNameStr[index];
+}
+
+const char *heap_status_name(int status)
+{
+ if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME))
+ return undefined;
+
+ int index = status - HEAP_DO_NOT_EXIST_YET;
+ return HeapStatusStr[index];
+}
/*
* Possible AGESA_STATUS values:
diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc
index 6b2ca78..ad39325 100644
--- a/src/northbridge/amd/agesa/family12/Makefile.inc
+++ b/src/northbridge/amd/agesa/family12/Makefile.inc
@@ -16,3 +16,6 @@
romstage-y += dimmSpd.c
ramstage-y += northbridge.c
+
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index c8198c9..4cffd61 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -632,24 +632,6 @@ static void domain_set_resources(device_t dev)
}
-static void domain_enable_resources(device_t dev)
-{
- printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
- /* Must be called after PCI enumeration and resource allocation */
-#if CONFIG_AMD_SB_CIMX
- sb_After_Pci_Init();
- sb_Mid_Post_Init();
-#endif
-
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
/* Bus related code */
static void cpu_bus_init(device_t dev)
@@ -790,7 +772,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = {
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
};
diff --git a/src/northbridge/amd/agesa/family12/state_machine.c b/src/northbridge/amd/agesa/family12/state_machine.c
new file mode 100644
index 0000000..bd71e14
--- /dev/null
+++ b/src/northbridge/amd/agesa/family12/state_machine.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include <cpu/amd/agesa/s3_resume.h>
+
+#include <sb_cimx.h>
+
+void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+ /* We use AMD_S3LATE_RESTORE instead. */
+ Post->MemConfig.SaveMemContextCtl = 0;
+ Post->MemConfig.MemRestoreCtl = 0;
+}
+
+void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+ EmptyHeap();
+
+ sb_before_pci_init();
+}
+
+void platform_AfterInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+ sb_After_Pci_Init();
+}
+
+void platform_AfterS3LateRestore(struct romstage_params *param, AMD_S3LATE_PARAMS *S3Late)
+{
+ OemS3LateRestore(AmdS3Late);
+
+ sb_After_Pci_Restore_Init();
+}
+
+void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid)
+{
+ sb_Mid_Post_Init();
+
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late)
+{
+ sb_Late_Post();
+}
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 6b2ca78..ad39325 100644
--- a/src/northbridge/amd/agesa/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
@@ -16,3 +16,6 @@
romstage-y += dimmSpd.c
ramstage-y += northbridge.c
+
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index b8d9c6f..bc517bd 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -614,30 +614,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
}
-static void domain_enable_resources(device_t dev)
-{
-#if CONFIG_AMD_SB_CIMX
- if (!acpi_is_wakeup_s3()) {
- sb_After_Pci_Init();
- sb_Mid_Post_Init();
- } else {
- sb_After_Pci_Restore_Init();
- }
-#endif
-
- /* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
-
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
-
- printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
-}
-
static const char *domain_acpi_name(struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -818,7 +794,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = {
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.acpi_name = domain_acpi_name,
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
new file mode 100644
index 0000000..d55c5dd
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include <cpu/amd/agesa/s3_resume.h>
+
+#include <sb_cimx.h>
+
+void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+ EmptyHeap();
+}
+
+void platform_BeforeInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+ OemInitResume(Resume);
+}
+
+void platform_AfterInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+ amd_initenv();
+
+ sb_After_Pci_Init();
+}
+
+void platform_AfterS3LateRestore(struct romstage_params *param, AMD_S3LATE_PARAMS *S3Late)
+{
+ OemS3LateRestore(AmdS3Late);
+
+ sb_After_Pci_Restore_Init();
+}
+
+void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid)
+{
+ sb_Mid_Post_Init();
+
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late)
+{
+ sb_Late_Post();
+}
+
+void platform_AfterS3Save(struct romstage_params *param, AMD_S3SAVE_PARAMS *S3Save)
+{
+ OemS3Save(AmdS3Save);
+}
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 9cfaed9..20cf7f9 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -632,21 +632,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(device_t dev)
-{
- /* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);
-
-#if CONFIG_AMD_SB_CIMX
- sb_After_Pci_Init();
-#endif
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__);
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -849,7 +834,6 @@ static void f15_pci_domain_scan_bus(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = f15_pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family15/state_machine.c b/src/northbridge/amd/agesa/family15/state_machine.c
new file mode 100644
index 0000000..9eba342
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/state_machine.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void platform_BeforeInitReset(struct romstage_params *param, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct romstage_params *param, AMD_POST_PARAMS *Post)
+{
+ /* We use AMD_S3LATE_RESTORE instead. */
+ Post->MemConfig.SaveMemContextCtl = 0;
+ Post->MemConfig.MemRestoreCtl = 0;
+}
+
+void platform_AfterInitPost(struct romstage_params *param, AMD_POST_PARAMS *Post)
+{
+ EmptyHeap();
+}
+
+void platform_AfterInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitEnv(struct romstage_params *param, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitLate(struct romstage_params *param, AMD_LATE_PARAMS *Late)
+{
+ cached_late_params = LateParams;
+}
diff --git a/src/northbridge/amd/agesa/family15rl/Makefile.inc b/src/northbridge/amd/agesa/family15rl/Makefile.inc
index a188a91..9e9283c 100644
--- a/src/northbridge/amd/agesa/family15rl/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15rl/Makefile.inc
@@ -17,3 +17,6 @@ romstage-y += dimmSpd.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
+
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c
index d003be5..8a85cf8 100644
--- a/src/northbridge/amd/agesa/family15rl/northbridge.c
+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c
@@ -629,21 +629,6 @@ static void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(struct device *dev)
-{
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3laterestore();
-
- /* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
- printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -842,7 +827,6 @@ static void domain_set_resources(struct device *dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family15rl/state_machine.c b/src/northbridge/amd/agesa/family15rl/state_machine.c
new file mode 100644
index 0000000..bd87fc0
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15rl/state_machine.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include <cpu/amd/agesa/s3_resume.h>
+
+void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+ EmptyHeap();
+}
+
+void platform_BeforeInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+ OemInitResume(Resume);
+}
+
+void platform_AfterInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterS3LateRestore(struct romstage_params *param, AMD_S3LATE_PARAMS *S3Late)
+{
+ amd_initcpuio();
+
+ OemS3LateRestore(AmdS3Late);
+
+ agesawrapper_fchs3earlyrestore();
+}
+
+void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid)
+{
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late)
+{
+ /* FIXME: not reached S3 path */
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3laterestore();
+}
+
+void platform_AfterS3Save(struct romstage_params *param, AMD_S3SAVE_PARAMS *S3Save)
+{
+ OemS3Save(AmdS3Save);
+}
diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc
index a188a91..9e9283c 100644
--- a/src/northbridge/amd/agesa/family15tn/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc
@@ -17,3 +17,6 @@ romstage-y += dimmSpd.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
+
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 2f05334..d487638 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -628,21 +628,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(device_t dev)
-{
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3laterestore();
-
- /* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
- printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -839,7 +824,6 @@ static void domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c
new file mode 100644
index 0000000..356e60b
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15tn/state_machine.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+
+void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+ EmptyHeap();
+}
+
+void platform_BeforeInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+ OemInitResume(Resume);
+}
+
+void platform_AfterInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterS3LateRestore(struct romstage_params *param, AMD_S3LATE_PARAMS *S3Late)
+{
+ amd_initcpuio();
+
+ OemS3LateRestore(AmdS3Late);
+
+ agesawrapper_fchs3earlyrestore();
+}
+
+void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid)
+{
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late)
+{
+ /* FIXME: not reached S3 path */
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3laterestore();
+}
+
+void platform_AfterS3Save(struct romstage_params *param, AMD_S3SAVE_PARAMS *S3Save)
+{
+ OemS3Save(AmdS3Save);
+}
diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc
index 3cf4ed1..3021ef4 100644
--- a/src/northbridge/amd/agesa/family16kb/Makefile.inc
+++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc
@@ -16,3 +16,6 @@
romstage-y += dimmSpd.c
ramstage-y += northbridge.c
+
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 28a4f91..f0a55c7 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -643,21 +643,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(device_t dev)
-{
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3laterestore();
-
- /* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
- printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -858,7 +843,6 @@ static void domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c
new file mode 100644
index 0000000..bd87fc0
--- /dev/null
+++ b/src/northbridge/amd/agesa/family16kb/state_machine.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include <cpu/amd/agesa/s3_resume.h>
+
+void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post)
+{
+ EmptyHeap();
+}
+
+void platform_BeforeInitResume(struct romstage_params *param, AMD_RESUME_PARAMS *Resume)
+{
+ OemInitResume(Resume);
+}
+
+void platform_AfterInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_AfterS3LateRestore(struct romstage_params *param, AMD_S3LATE_PARAMS *S3Late)
+{
+ amd_initcpuio();
+
+ OemS3LateRestore(AmdS3Late);
+
+ agesawrapper_fchs3earlyrestore();
+}
+
+void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid)
+{
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late)
+{
+ /* FIXME: not reached S3 path */
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3laterestore();
+}
+
+void platform_AfterS3Save(struct romstage_params *param, AMD_S3SAVE_PARAMS *S3Save)
+{
+ OemS3Save(AmdS3Save);
+}
diff --git a/src/northbridge/amd/agesa/state_machine.c b/src/northbridge/amd/agesa/state_machine.c
new file mode 100644
index 0000000..af6ca17
--- /dev/null
+++ b/src/northbridge/amd/agesa/state_machine.c
@@ -0,0 +1,341 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <arch/acpi.h>
+#include <bootstate.h>
+#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "amdlib.h"
+#include <cpu/amd/agesa/s3_resume.h>
+
+#include "AMD.h"
+#include "heapManager.h"
+
+#if ENV_RAMSTAGE
+static void completion_InitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late);
+#endif
+
+
+static AGESA_STATUS amd_alloc(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func)
+{
+ p->StdHeader.Func = AMD_CREATE_STRUCT;
+ p->AgesaFunctionName = func;
+ p->AllocationMethod = 0;
+ p->NewStructPtr = NULL;
+ p->NewStructSize = 0;
+ return AmdAgesaDispatcher(p);
+}
+
+static AGESA_STATUS amd_release(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func)
+{
+ /* Cannot release AMD_LATE_PARAMS until ACPI tables are done. */
+ if (func == AMD_INIT_LATE)
+ return AGESA_SUCCESS;
+
+ p->StdHeader.Func = AMD_RELEASE_STRUCT;
+ p->AgesaFunctionName = func;
+ p->AllocationMethod = 0;
+ return AmdAgesaDispatcher(p);
+}
+
+static AGESA_STATUS amd_alloc_stack(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func, void *buf, size_t len)
+{
+ /* By design, each valid AGESA_STRUCT_NAME
+ * can be casted to AMD_CONFIG_PARAMS.
+ */
+ AMD_CONFIG_PARAMS *call = buf;
+ memset(call, 0, len);
+
+ p->StdHeader.Func = AMD_CREATE_STRUCT;
+ p->AgesaFunctionName = func;
+ p->AllocationMethod = ByHost;
+ p->NewStructPtr = call;
+ p->NewStructSize = len;
+
+ /* AMD_CREATE_STRUCT with ByHost skips this. */
+ *call = p->StdHeader;
+
+ return AmdAgesaDispatcher(p);
+}
+
+static AGESA_STATUS amd_release_stack(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func)
+{
+ p->StdHeader.Func = AMD_RELEASE_STRUCT;
+ p->AgesaFunctionName = func;
+ p->AllocationMethod = ByHost;
+ return AmdAgesaDispatcher(p);
+}
+
+static AGESA_STATUS amd_dispatch(AMD_CONFIG_PARAMS *call, struct agesa_state *cfg)
+{
+ /* By design, for each valid AGESA_STRUCT_NAME, AMD_CONFIG_PARAMS
+ * can be evaluated to apply correct typecast based on Func field.
+ */
+
+ switch (call->Func)
+ {
+#if ENV_ROMSTAGE
+ case AMD_INIT_RESET:
+ {
+ AMD_RESET_PARAMS *param = (void *)call;
+ platform_BeforeInitReset(cfg->romstage, param);
+ cfg->status = AmdAgesaDispatcher(call);
+ break;
+ }
+
+ case AMD_INIT_EARLY:
+ {
+ AMD_EARLY_PARAMS *param = (void *)call;
+ platform_BeforeInitEarly(cfg->romstage, param);
+ board_BeforeInitEarly(cfg->romstage, param);
+ cfg->status = AmdAgesaDispatcher(call);
+ break;
+ }
+
+ case AMD_INIT_POST:
+ {
+ AMD_POST_PARAMS *param = (void *)call;
+ platform_BeforeInitPost(cfg->romstage, param);
+ board_BeforeInitPost(cfg->romstage, param);
+ cfg->status = AmdAgesaDispatcher(call);
+ platform_AfterInitPost(cfg->romstage, param);
+ break;
+ }
+
+ case AMD_INIT_RESUME:
+ {
+ AMD_RESUME_PARAMS *param = (void *)call;
+ platform_BeforeInitResume(cfg->romstage, param);
+ cfg->status = AmdAgesaDispatcher(call);
+ break;
+ }
+
+ case AMD_INIT_ENV:
+ {
+ AMD_ENV_PARAMS *param = (void *)call;
+ cfg->status = AmdAgesaDispatcher(call);
+ platform_AfterInitEnv(cfg->romstage, param);
+ break;
+ }
+
+ case AMD_S3LATE_RESTORE:
+ {
+ AMD_S3LATE_PARAMS *param = (void *)call;
+ platform_BeforeS3LateRestore(cfg->romstage, param);
+ cfg->status = AmdAgesaDispatcher(call);
+ break;
+ }
+#endif
+#if ENV_RAMSTAGE
+ case AMD_INIT_MID:
+ {
+ AMD_MID_PARAMS *param = (void *)call;
+ platform_BeforeInitMid(cfg->ramstage, param);
+ board_BeforeInitMid(cfg->ramstage, param);
+ cfg->status = AmdAgesaDispatcher(call);
+ break;
+ }
+
+ case AMD_S3_SAVE:
+ {
+ AMD_S3SAVE_PARAMS *param = (void *)call;
+ cfg->status = AmdAgesaDispatcher(call);
+ platform_AfterS3Save(cfg->ramstage, param);
+ break;
+ }
+ case AMD_INIT_LATE:
+ {
+ AMD_LATE_PARAMS *param = (void *)call;
+ cfg->status = AmdAgesaDispatcher(call);
+ platform_AfterInitLate(cfg->ramstage, param);
+ completion_InitLate(cfg->ramstage, param);
+ break;
+ }
+#endif
+ default:
+ {
+ cfg->status = AGESA_UNSUPPORTED;
+ break;
+ }
+
+ }
+ return cfg->status;
+}
+
+static void state_on_entry(struct agesa_state *params, AGESA_STRUCT_NAME func)
+{
+ params->func = func;
+ params->function_name = agesa_struct_name(func);
+
+ printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n",
+ params->apic_id, params->function_name, params->func);
+}
+
+static void state_on_exit(struct agesa_state *params)
+{
+ AMD_INTERFACE_PARAMS *mm = params->amd_interface_params;
+ AMD_CONFIG_PARAMS *call = &mm->StdHeader;
+
+ agesawrapper_trace(params->status, call, params->function_name);
+
+ printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n",
+ params->apic_id, heap_status_name(call->HeapStatus), call->HeapStatus,
+ (u32)call->HeapBasePtr);
+
+ printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n",
+ params->apic_id, params->function_name, params->func);
+}
+
+//int agesa_execute_state(struct agesa_state *params, AGESA_STRUCT_NAME func)
+int agesa_execute_state(struct agesa_state *params, int func)
+{
+ AMD_INTERFACE_PARAMS *mm = params->amd_interface_params;
+ AMD_RESET_PARAMS reset;
+ AGESA_STATUS status;
+
+ state_on_entry(params, func);
+
+ if (func == AMD_INIT_RESET)
+ status = amd_alloc_stack(mm, func, &reset, sizeof(reset));
+ else
+ status = amd_alloc(mm, func);
+ ASSERT(status == AGESA_SUCCESS);
+
+ AMD_CONFIG_PARAMS *call = mm->NewStructPtr;
+ /* Must call the function buffer was allocated for.*/
+ ASSERT(call->Func == func);
+
+ status = amd_dispatch(call, params);
+ ASSERT(status < AGESA_FATAL);
+
+ if (func == AMD_INIT_RESET)
+ status = amd_release_stack(mm, func);
+ else
+ status = amd_release(mm, func);
+ ASSERT(status == AGESA_SUCCESS);
+
+ state_on_exit(params);
+
+ return 0;
+}
+
+#if ENV_RAMSTAGE
+
+static struct agesa_state state_machine;
+static AMD_INTERFACE_PARAMS amd_interface_params;
+static AMD_INTERFACE_PARAMS *aip = NULL;
+
+static void agesa_mid(void *unused)
+{
+ memset(&amd_interface_params, 0, sizeof(AMD_INTERFACE_PARAMS));
+ aip = &amd_interface_params;
+ aip->StdHeader.CalloutPtr = GetBiosCallout;
+
+ state_machine.amd_interface_params = aip;
+ if (!acpi_is_wakeup_s3())
+ agesa_execute_state(&state_machine, AMD_INIT_MID);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, agesa_mid, NULL);
+
+static void agesa_late(void *unused)
+{
+ if (acpi_is_wakeup_s3())
+ return;
+
+ agesa_execute_state(&state_machine, AMD_INIT_LATE);
+
+ if (!acpi_s3_resume_allowed())
+ return;
+
+ agesa_execute_state(&state_machine, AMD_S3_SAVE);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesa_late, NULL);
+
+
+/* We will reference AmdLateParams later to copy ACPI tables. */
+static AMD_LATE_PARAMS *AmdLateParams;
+
+static void completion_InitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late)
+{
+ AmdLateParams = Late;
+}
+
+void *agesawrapper_getlateinitptr(int pick)
+{
+ ASSERT(AmdLateParams != NULL);
+
+ switch (pick) {
+ case PICK_DMI:
+ return AmdLateParams->DmiTable;
+ case PICK_PSTATE:
+ return AmdLateParams->AcpiPState;
+ case PICK_SRAT:
+ return AmdLateParams->AcpiSrat;
+ case PICK_SLIT:
+ return AmdLateParams->AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AmdLateParams->AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AmdLateParams->AcpiWheaCmc;
+ case PICK_ALIB:
+ return AmdLateParams->AcpiAlib;
+ case PICK_IVRS:
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14)
+ return NULL;
+#else
+ return AmdLateParams->AcpiIvrs;
+#endif
+ default:
+ return NULL;
+ }
+ return NULL;
+}
+
+#endif /* ENV_RAMSTAGE */
+
+AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
+{
+#if 0
+ AGESA_STATUS status;
+ AP_EXE_PARAMS ApExeParams;
+
+ memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
+ ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout;
+
+ ApExeParams.FunctionNumber = Func;
+ ApExeParams.RelatedDataBlock = ConfigPtr;
+
+ status = AmdLateRunApTask(&ApExeParams);
+ AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
+ ASSERT(status == AGESA_SUCCESS);
+
+ return status;
+#else
+ return AGESA_SUCCESS;
+#endif
+}
+
+#if 0
+void __attribute__((weak)) board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *p) { }
+void __attribute__((weak)) board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *p) { }
+void __attribute__((weak)) board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p) { }
+#endif
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h
new file mode 100644
index 0000000..9a76d3c
--- /dev/null
+++ b/src/northbridge/amd/agesa/state_machine.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _STATE_MACHINE_H_
+#define _STATE_MACHINE_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+ PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */
+};
+
+AGESA_STATUS agesawrapper_amdinitlate(void);
+AGESA_STATUS agesawrapper_amdinitmid(void);
+
+const char *agesa_struct_name(int state);
+const char *heap_status_name(int status);
+void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func);
+
+void amd_initcpuio(void);
+void amd_initmmio(void);
+void amd_initenv(void);
+
+AGESA_STATUS agesawrapper_amdS3Save(void);
+AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+void *agesawrapper_getlateinitptr (int pick);
+
+AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
+AGESA_STATUS agesawrapper_fchs3laterestore(void);
+
+struct OEM_HOOK
+{
+ /* romstage */
+ AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *);
+ AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *);
+
+ /* ramstage */
+ AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *);
+};
+
+extern const struct OEM_HOOK OemCustomize;
+
+/* For suspend-to-ram support. */
+AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams);
+AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams);
+AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams);
+
+
+#endif /* _STATE_MACHINE_H_ */
diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c
index 00c6518..6a1004b 100644
--- a/src/southbridge/amd/agesa/hudson/agesawrapper.c
+++ b/src/southbridge/amd/agesa/hudson/agesawrapper.c
@@ -35,8 +35,6 @@
#include <device/device.h>
#include "hudson.h"
-extern UINT8 picr_data[0x54], intr_data[0x54];
-
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#error Use of GetHeapBase() is incorrect or at least suspicious
#endif
@@ -76,17 +74,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore (void)
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index 1701a21..7c16f7a 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1245,7 +1245,7 @@ fam15_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- wbinvd # Clear the cache tag RAMs
+ invd # Clear the cache tag RAMs
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
cmp $01, %bh
jz 4f
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 87e6090..6d3f4d1 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -597,8 +597,7 @@ fam16_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- wbinvd # Clear the cache tag RAMs
- #invd
+ invd # Clear the cache tag RAMs
#Do Standard Family 16 work
mov $HWCR, %ecx # MSR:C001_0015h
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