[coreboot-gerrit] New patch to review for coreboot: [Don't merge] dynamic ASL for SD Card test patch
Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)
gerrit at coreboot.org
Fri Mar 3 00:08:42 CET 2017
Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18550
-gerrit
commit 4ad9ae80a14bc9c9da2c979ffbfd403c8581ed30
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date: Thu Mar 2 11:36:11 2017 -0800
[Don't merge] dynamic ASL for SD Card test patch
Change-Id: I995447994893f4f0e7864743dac7ae7bdcc8fd14
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
src/arch/x86/acpi_device.c | 3 +
.../google/reef/variants/baseboard/devicetree.cb | 2 +-
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/acpi.c | 14 +++-
src/soc/intel/apollolake/acpi/scs.asl | 19 ++++-
src/soc/intel/apollolake/chip.c | 15 ++++
src/soc/intel/apollolake/chip.h | 24 +++++-
src/soc/intel/apollolake/sd.c | 98 ++++++++++++++++++++++
8 files changed, 166 insertions(+), 10 deletions(-)
diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
index 42305a6..d603111 100644
--- a/src/arch/x86/acpi_device.c
+++ b/src/arch/x86/acpi_device.c
@@ -228,8 +228,10 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio)
uint16_t flags = 0;
int pin;
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 7.0 gpio address=%x, type=%d\n", !gpio, gpio->type);
if (!gpio || gpio->type > ACPI_GPIO_TYPE_IO)
return;
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 7.1\n");
start = acpigen_get_current();
@@ -262,6 +264,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio)
* [2:1]: Polarity (0=HIGH 1=LOW 2=BOTH)
* [0]: Mode (0=LEVEL 1=EDGE)
*/
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 7.2\n");
if (gpio->irq.mode == ACPI_IRQ_EDGE_TRIGGERED)
flags |= 1 << 0;
if (gpio->irq.shared == ACPI_IRQ_SHARED)
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 443918e..164d646 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -18,7 +18,7 @@ chip soc/intel/apollolake
register "prt0_gpio" = "GPIO_122"
# GPIO for SD card detect
- register "sdcard_cd_gpio" = "GPIO_177"
+ register "sdcard_cd_gpio_default" = "GPIO_177"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index df93f0b..bfe4273 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -84,6 +84,7 @@ ramstage-y += smi.c
ramstage-y += sram.c
ramstage-y += spi.c
ramstage-y += xhci.c
+ramstage-y += sd.c
postcar-y += flash_ctrlr.c
postcar-y += memmap.c
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 6aa985d..b7b0e56 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -184,9 +184,17 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
- /* Assign Gpio address of SDCARD Card detect */
- gnvs->sdcd = (uintptr_t)gpio_dwx_address(cfg->sdcard_cd_gpio);
-
+ /* Nothing to write if GPIO is not set in devicetree */
+ if (!cfg->sdcard_cd_gpio_default && !cfg->sdcard_cd_gpio.pins[0])
+ {
+ printk(BIOS_ERR, "Venkat: SDCARD Card detect not defined\n");
+ return;
+ }
+ else
+ { /* Assign Gpio address of SDCARD Card detect */
+ gnvs->sdcd = (uintptr_t)gpio_dwx_address(cfg->sdcard_cd_gpio_default);
+ printk(BIOS_ERR, "Venkat: SDCARD Card detect gnvs_address=%x, gpio_default=%d\n", gnvs->sdcd, cfg->sdcard_cd_gpio_default);
+ }
}
/* Save wake source information for calculating ACPI _SWS values */
diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
index cc157e2..041c2f1 100644
--- a/src/soc/intel/apollolake/acpi/scs.asl
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -27,6 +27,13 @@ Scope (\_SB.PCI0) {
GRR3, 1, /* GPPRVRW3 used for SD Card detect Bypass. */
}
+ OperationRegion (POST, SystemIO, 0x80, 1)
+ Field (POST, ByteAcc, Lock, Preserve)
+ {
+ DBG0, 8
+ }
+
+
/* SCC power gate control method, this method must be serialized as
* multiple device will control the GENR register
*
@@ -69,10 +76,11 @@ Scope (\_SB.PCI0) {
} /* Device (SDHA) */
/* SD CARD */
- Device (SDC)
+ Device (SDCD)
{
Name (_ADR, 0x001B0000)
+#if 0
Name (RBUF, ResourceTemplate ()
{
GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 0,
@@ -83,7 +91,7 @@ Scope (\_SB.PCI0) {
{
Return (RBUF)
}
-
+#endif
OperationRegion (PCCS, PCI_Config, 0x84, 0x04)
Field (PCCS, WordAcc, NoLock, Preserve) {
PMSR, 32 /* 4h: Power Gating Control */
@@ -91,6 +99,7 @@ Scope (\_SB.PCI0) {
Method (_PS0, 0, NotSerialized)
{
+ Store(0xD0,DBG0)
/* Store DW0 into local1 */
Store (\_SB.GPC0 (\SDCD), Local1)
/* Extract rxstate [bit 1] of sdcard card detect pin */
@@ -99,20 +108,24 @@ Scope (\_SB.PCI0) {
* If sdcard is not present, rxstate is High.
* Write the inverted value of rxstate to GRR3.
*/
+ Store(Local1,DBG0)
Not (Local1, \_SB.PCI0.GRR3)
+ Store(GRR3,DBG0)
/* Disable power gate by clearing bit 1 and 0 */
And (^PMSR, 0xFFFFFFFC, ^PMSR)
/* Sleep 2 ms */
Sleep (2)
+ Store(0xD0,DBG0)
}
Method (_PS3, 0, NotSerialized)
{
+ Store(0xD1,DBG0)
/* Enable power gate by restore bit 1 and 0 */
Store (0, \_SB.PCI0.GRR3)
Or (^PMSR, 0x3, ^PMSR)
}
- } /* Device (SDC) */
+ } /* Device (SDCD) */
}
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1de41cf..48febf9 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -113,6 +113,21 @@ static const char *soc_acpi_name(struct device *dev)
return NULL;
}
+static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device)
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ else
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ (device << 16) | vendor);
+}
+
+struct pci_operations soc_pci_ops = {
+ .set_subsystem = &pci_set_subsystem
+};
+
+
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 22d3b4e..bc0ea79 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -18,6 +18,7 @@
#ifndef _SOC_APOLLOLAKE_CHIP_H_
#define _SOC_APOLLOLAKE_CHIP_H_
+#include <arch/acpi_device.h>
#include <soc/gpe.h>
#include <soc/gpio_defs.h>
#include <soc/gpio.h>
@@ -117,12 +118,29 @@ struct soc_intel_apollolake_config {
/* GPIO pin for PERST_0 */
uint16_t prt0_gpio;
- /* GPIO pin for SDCARD Card Detect */
- uint16_t sdcard_cd_gpio;
-
/* USB2 eye diagram settings per port */
struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX];
+ /*
+ * Use SD card detect GPIO with default config:
+ * - Edge triggered
+ * - No internal pull
+ * - Active both (high + low)
+ * - Can wake device from D3
+ * - 100ms debounce timeout
+ *
+ * GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
+ * "\\_SB.PCI0.GPIO", 0, ResourceConsumer)
+ * { sdcard_cd_gpio_default }
+ */
+ unsigned sdcard_cd_gpio_default;
+
+ /* Use custom SD card detect GPIO configuration */
+ struct acpi_gpio sdcard_cd_gpio;
+
};
+typedef struct soc_intel_apollolake_config config_t;
+
+extern struct pci_operations soc_pci_ops;
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c
new file mode 100644
index 0000000..2548ca3
--- /dev/null
+++ b/src/soc/intel/apollolake/sd.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include "chip.h"
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static void sd_fill_ssdt(struct device *dev)
+{
+ config_t *config = dev->chip_info;
+ const char *path;
+ struct acpi_gpio default_gpio = {
+ .type = ACPI_GPIO_TYPE_INTERRUPT,
+ .pull = ACPI_GPIO_PULL_NONE,
+ .irq.mode = ACPI_IRQ_EDGE_TRIGGERED,
+ .irq.polarity = ACPI_IRQ_ACTIVE_BOTH,
+ .irq.shared = ACPI_IRQ_SHARED,
+ .irq.wake = ACPI_IRQ_WAKE,
+ .interrupt_debounce_timeout = 10000, /* 100ms */
+ .pin_count = 1,
+ .pins = { config->sdcard_cd_gpio_default }
+ };
+ struct acpi_dp *dp;
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 1\n");
+ if (!dev->enabled)
+ return;
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 2\n");
+
+ /* Nothing to write if GPIO is not set in devicetree */
+ if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0])
+ return;
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 3\n");
+
+ /* Use device path as the Scope for the SSDT */
+ path = acpi_device_path(dev);
+ if (!path)
+ return;
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 4\n");
+ acpigen_write_scope(path);
+ acpigen_write_name("_CRS");
+
+ /* Write GpioInt() as default (if set) or custom from devicetree */
+ acpigen_write_resourcetemplate_header();
+ if (config->sdcard_cd_gpio_default)
+ {
+ acpi_device_write_gpio(&default_gpio);
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 7\n");
+ }
+ else
+ {
+ acpi_device_write_gpio(&config->sdcard_cd_gpio);
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 8\n");
+ }
+ acpigen_write_resourcetemplate_footer();
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 5\n");
+
+ /* Bind the cd-gpio name to the GpioInt() resource */
+ dp = acpi_dp_new_table("_DSD");
+ acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
+ acpi_dp_write(dp);
+ printk(BIOS_ERR, "Venkat: ASL Dynamic code 6\n");
+
+ acpigen_pop_len();
+}
+#endif
+
+static struct device_operations dev_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .ops_pci = &soc_pci_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt_generator = &sd_fill_ssdt,
+#endif
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+ .ops = &dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x5aca
+};
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