[coreboot-gerrit] Change in coreboot[master]: rockchip/rk3399: update the ddr 200M frequency configure
Caesar Wang (Code Review)
gerrit at coreboot.org
Thu Jun 22 10:28:11 CEST 2017
Caesar Wang has uploaded this change for review. ( https://review.coreboot.org/20304
Change subject: rockchip/rk3399: update the ddr 200M frequency configure
......................................................................
rockchip/rk3399: update the ddr 200M frequency configure
This patch update configure that's for unifying between the coreboot and
ARM TF, as this configure is different with the ATF's ddr configure.
Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Signed-off-by: Caesar Wang <wxt at rock-chips.com>
---
M src/soc/rockchip/rk3399/clock.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/20304/1
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 35c96bc..980adf5 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -636,7 +636,7 @@
switch (hz) {
case 200*MHz:
dpll_cfg = (struct pll_div)
- {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
+ {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2};
break;
case 300*MHz:
dpll_cfg = (struct pll_div)
--
To view, visit https://review.coreboot.org/20304
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Gerrit-Change-Number: 20304
Gerrit-PatchSet: 1
Gerrit-Owner: Caesar Wang <wxt at rock-chips.com>
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