[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Move ACPI madt table to soc
Marc Jones (Code Review)
gerrit at coreboot.org
Tue Jun 20 07:59:37 CEST 2017
Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20277
Change subject: soc/amd/stoneyridge: Move ACPI madt table to soc
......................................................................
soc/amd/stoneyridge: Move ACPI madt table to soc
Move the mainboard madt tables to generic soc ACPI code.
Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/amd/gardenia/acpi_tables.c
M src/mainboard/google/kahlee/acpi_tables.c
M src/soc/amd/stoneyridge/acpi.c
3 files changed, 31 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/20277/1
diff --git a/src/mainboard/amd/gardenia/acpi_tables.c b/src/mainboard/amd/gardenia/acpi_tables.c
index 1b4f90c..8d4d1cf 100644
--- a/src/mainboard/amd/gardenia/acpi_tables.c
+++ b/src/mainboard/amd/gardenia/acpi_tables.c
@@ -1,8 +1,4 @@
/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -13,46 +9,6 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdfam16.h>
-
-#define IO_APIC2_ADDR 0xFEC20000
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write Kern IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
- IO_APIC_ADDR, 0);
-
- /* TODO: Remove the hardcode */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
- IO_APIC2_ADDR, 24);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/mainboard/google/kahlee/acpi_tables.c b/src/mainboard/google/kahlee/acpi_tables.c
index 1b4f90c..8d4d1cf 100644
--- a/src/mainboard/google/kahlee/acpi_tables.c
+++ b/src/mainboard/google/kahlee/acpi_tables.c
@@ -1,8 +1,4 @@
/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -13,46 +9,6 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdfam16.h>
-
-#define IO_APIC2_ADDR 0xFEC20000
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write Kern IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
- IO_APIC_ADDR, 0);
-
- /* TODO: Remove the hardcode */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
- IO_APIC2_ADDR, 24);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 34164f4..1e03d50 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -23,6 +23,7 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cbmem.h>
#include <device/device.h>
#include <soc/acpi.h>
@@ -30,7 +31,31 @@
#include <soc/nvs.h>
#include <soc/smi.h>
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+ /* Write Kern IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
/*
* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
* in the ACPI 3.0b specification.
--
To view, visit https://review.coreboot.org/20277
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb
Gerrit-Change-Number: 20277
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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