[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Add ec and gnvs ACPI

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20276


Change subject: google/kahlee: Add ec and gnvs ACPI
......................................................................

google/kahlee: Add ec and gnvs ACPI

Add ACPI support for the Google EC, which requires gnvs support
for passing information from the EC to firmware and OS.

Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones at scarletltd.com>
---
A src/mainboard/google/kahlee/acpi/ec.asl
A src/mainboard/google/kahlee/acpi/superio.asl
M src/mainboard/google/kahlee/dsdt.asl
M src/mainboard/google/kahlee/ec.c
M src/mainboard/google/kahlee/ec.h
5 files changed, 62 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/20276/1

diff --git a/src/mainboard/google/kahlee/acpi/ec.asl b/src/mainboard/google/kahlee/acpi/ec.asl
new file mode 100644
index 0000000..8f59cb5
--- /dev/null
+++ b/src/mainboard/google/kahlee/acpi/ec.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "ec.h"
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+/*
+ * There is no GPIO for LID, the EC pulses WAKE# pin instead.
+ * There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE.
+ */
+#define EC_ENABLE_WAKE_PIN	0x69
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/kahlee/acpi/superio.asl b/src/mainboard/google/kahlee/acpi/superio.asl
new file mode 100644
index 0000000..b3e9afc
--- /dev/null
+++ b/src/mainboard/google/kahlee/acpi/superio.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/kahlee/ec.h>
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+#define SIO_EC_ENABLE_COM1       // Enable Serial Port 1
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 871fcd2..1239f57 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -23,7 +23,11 @@
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
+	/* Include global debug methods if needed */
+	/* #include <arch/x86/acpi/debug.asl> */
+
+	/* global NVS and variables */
+	#include <soc/intel/broadwell/acpi/globalnvs.asl>
 
 	/* Globals for the platform */
 	#include "acpi/mainboard.asl"
@@ -74,6 +78,9 @@
 
 	} /* End \_SB scope */
 
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
 	/* Describe SMBUS for the Southbridge */
 	#include <soc/amd/stoneyridge/acpi/smbus.asl>
 
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
index da0f855..71c6e10 100644
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -15,6 +15,7 @@
 
 #include <arch/acpi.h>
 #include <console/console.h>
+#include <ec/google/chromeec/ec.h>
 #include "ec.h"
 #include <rules.h>
 #include <soc/hudson.h>
diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h
index bf4e3ad..6340b69 100644
--- a/src/mainboard/google/kahlee/ec.h
+++ b/src/mainboard/google/kahlee/ec.h
@@ -17,7 +17,6 @@
 #define MAINBOARD_EC_H
 
 #include <ec/ec.h>
-#include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 
 /* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Gerrit-Change-Number: 20276
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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