[coreboot-gerrit] Change in coreboot[master]: [WIP]: add superio driver for sch5545
Alexander Couzens (Code Review)
gerrit at coreboot.org
Fri Jun 16 20:13:44 CEST 2017
Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/20238
Change subject: [WIP]: add superio driver for sch5545
......................................................................
[WIP]: add superio driver for sch5545
based on a sch5627 datasheet which is similiar (id 0xc4 <> 0xc6)
Change-Id: Ic258630b02e6ae86b1ee7ce663d9d026bf1c04e9
Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
M src/superio/smsc/Makefile.inc
A src/superio/smsc/sch5545/Kconfig
A src/superio/smsc/sch5545/Makefile.inc
A src/superio/smsc/sch5545/sch5545.h
A src/superio/smsc/sch5545/sch5545_early_init.c
A src/superio/smsc/sch5545/superio.c
6 files changed, 288 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/20238/1
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index 9b86745..977ea23 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -30,3 +30,4 @@
subdirs-y += smscsuperio
subdirs-y += sio1036
subdirs-y += sch4037
+subdirs-y += sch5545
diff --git a/src/superio/smsc/sch5545/Kconfig b/src/superio/smsc/sch5545/Kconfig
new file mode 100644
index 0000000..71116bd
--- /dev/null
+++ b/src/superio/smsc/sch5545/Kconfig
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Alexander Couzens <lynxis at fe80.eu>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_SMSC_SCH5545
+ bool
diff --git a/src/superio/smsc/sch5545/Makefile.inc b/src/superio/smsc/sch5545/Makefile.inc
new file mode 100644
index 0000000..5513392
--- /dev/null
+++ b/src/superio/smsc/sch5545/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Alexander Couzens <lynxis at fe80.eu>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-$(CONFIG_SUPERIO_SMSC_SCH5545) += sch5545_early_init.c
+ramstage-$(CONFIG_SUPERIO_SMSC_SCH5545) += superio.c
diff --git a/src/superio/smsc/sch5545/sch5545.h b/src/superio/smsc/sch5545/sch5545.h
new file mode 100644
index 0000000..9be7d5e
--- /dev/null
+++ b/src/superio/smsc/sch5545/sch5545.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_SCH_5545_H
+#define SUPERIO_SCH_5545_H
+
+/* LPC i/o space */
+#define SCH5545_RUNTIME_REG_BASE 0x0a00
+
+/* runtime register */
+#define SCH5545_RR_LED 0x25
+/* bit 0-1 blink */
+#define SCH5545_LED_BLINK_OFF 0x0
+#define SCH5545_LED_BLINK_1HZ 0x1
+#define SCH5545_LED_BLINK_ON 0x3
+#define SCH5545_LED_BLINK_MASK 0x3
+/* bit 2 color */
+#define SCH5545_LED_COLOR_YELLOW 0x0
+#define SCH5545_LED_COLOR_GREEN 0x4
+#define SCH5545_LED_CODE_FETCH 0x8
+
+/* logical devices */
+#define SCH5545_LDN_UART1 0x07
+#define SCH5545_LDN_UART2 0x08
+#define SCH5545_LDN_LPC_IF 0x0c /* LPC Interface */
+
+/* UART config registers */
+#define SCH5545_CONFIG_SELECT 0xf0
+
+/* UART config select */
+#define SCH5545_UART_POWER_VCC 0x02
+#define SCH5545_UART_INVERT_POLARITY 0x04
+
+/* LPC IF config registers */
+#define SCH5545_IRQ_BASE 0x40
+
+/*
+ * BAR registers are 4 byte
+ * byte 0 0-6 mask, 7 reserved
+ * byte 1 0-5 frame, 6 device, 7 valid
+ * byte 2 LPC address least sig.
+ * byte 3 LPC address most sig.
+ */
+#define SCH5545_BAR_LPC_IF 0x60
+#define SCH5545_BAR_EM_IF 0x64
+#define SCH5545_BAR_UART1 0x68
+#define SCH5545_BAR_UART2 0x6c
+#define SCH5545_BAR_RUNTIME_REG 0x70
+/* missing ? */
+#define SCH5545_BAR_FLOPPY 0x78
+#define SCH5545_BAR_PARPORT 0x80
+
+/* IRQ <> device mappings */
+#define SCH5545_IRQ_KBD 0x01
+#define SCH5545_IRQ_MOUSE 0x81
+#define SCH5545_IRQ_UART1 0x07
+#define SCH5545_IRQ_UART2 0x08
+#define SCH5545_IRQ_EMI_MAILBOX 0x00
+#define SCH5545_IRQ_EMI_IRQ_SOURCE 0x80
+#define SCH5545_IRQ_RUNTIME_REG 0x0a
+#define SCH5545_IRQ_RUNTIME_REG_SMI 0x8a
+#define SCH5545_IRQ_FLOPPY 0x0b
+#define SCH5545_IRQ_PARPORT 0x11
+#define SCH5545_IRQ_DISABLED 0xff
+
+void sch5545_early_init(unsigned port);
+void sch5545_set_led(unsigned runtime_reg_base, unsigned color, uint16_t blink);
+
+#endif /* SUPERIO_SCH_5545_H */
diff --git a/src/superio/smsc/sch5545/sch5545_early_init.c b/src/superio/smsc/sch5545/sch5545_early_init.c
new file mode 100644
index 0000000..2c48cba
--- /dev/null
+++ b/src/superio/smsc/sch5545/sch5545_early_init.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include "sch5545.h"
+
+static void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+ unsigned port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+ unsigned port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/*
+ * Set the BAR / iobase for a specific device.
+ * pnp_devfn_t dev must be in conf state.
+ * LDN LPC IF must be active.
+ */
+static void sch5545_set_iobase(pnp_devfn_t dev, uint16_t device_addr, uint32_t bar_addr)
+{
+ uint8_t val;
+ unsigned port = dev >> 8;
+
+ pnp_devfn_t lpcif = PNP_DEV(port, SCH5545_LDN_LPC_IF);
+ pnp_set_logical_device(lpcif);
+
+ /* set BAR */
+ pnp_set_iobase(dev, device_addr + 2, bar_addr);
+
+ /* set valid */
+ val = pnp_read_config(dev, device_addr + 1);
+ val |= 0x80;
+ pnp_write_config(dev, device_addr + 1, val);
+
+ pnp_set_logical_device(dev);
+}
+
+/*
+ * set the IRQ for the specific device
+ * pnp_devfn_t dev must be in conf state
+ * LDN LPC IF must be active.
+ */
+static void sch5545_set_irq(pnp_devfn_t dev, uint8_t irq_device, unsigned irq)
+{
+ unsigned port = dev >> 8;
+ if (irq > 15)
+ return;
+
+ pnp_devfn_t lpcif = PNP_DEV(port, SCH5545_LDN_LPC_IF);
+ pnp_set_logical_device(lpcif);
+ pnp_write_config(dev, SCH5545_IRQ_BASE + irq, irq_device);
+ pnp_set_logical_device(dev);
+}
+
+/* sch5545 has 2 LEDs which are accessed via color (1 bit),
+ * 2 bits for a pattern blink
+ * 1 bit for "code fetch" which means the cpu/mainboard is working (always set)
+ */
+void sch5545_set_led(unsigned runtime_reg_base, unsigned color, uint16_t blink)
+{
+ uint8_t val = blink && SCH5545_LED_BLINK_MASK;
+ val |= SCH5545_LED_CODE_FETCH;
+ if (color)
+ val |= SCH5545_LED_COLOR_GREEN;
+ outb(val, runtime_reg_base + SCH5545_RR_LED);
+}
+
+void sch5545_early_init(unsigned port)
+{
+ pnp_devfn_t dev;
+
+
+ /* enable lpc if */
+ dev = PNP_DEV(port, SCH5545_LDN_LPC_IF);
+ pnp_enter_conf_state(dev);
+
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 1);
+
+ /* map runtime register */
+ sch5545_set_iobase(dev,
+ SCH5545_BAR_RUNTIME_REG,
+ SCH5545_RUNTIME_REG_BASE);
+
+ /* configure serial 1 / UART 1 */
+ dev = PNP_DEV(port, SCH5545_LDN_UART1);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 1);
+ pnp_write_config(dev, SCH5545_CONFIG_SELECT, SCH5545_UART_POWER_VCC);
+ sch5545_set_iobase(dev, SCH5545_BAR_UART1, CONFIG_TTYS0_BASE);
+ sch5545_set_irq(dev, SCH5545_IRQ_UART1, 4);
+
+ /* set SCH5545_LED_CODE_FETCH + blink orange = 1hz */
+ sch5545_set_led(SCH5545_RUNTIME_REG_BASE, SCH5545_LED_COLOR_YELLOW, SCH5545_LED_BLINK_1HZ);
+
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c
new file mode 100644
index 0000000..469335c
--- /dev/null
+++ b/src/superio/smsc/sch5545/superio.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+
+#include "sch5545.h"
+/*
+static void sch5545_init(struct device *dev)
+{
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = sch5545_init,
+ .ops_pnp_mode = &pnp_conf_mode_55_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, SCH5545_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_smsc_sch5545_ops = {
+ CHIP_NAME("SMSC SCH5545 Super I/O")
+ .enable_dev = enable_dev,
+};
+*/
--
To view, visit https://review.coreboot.org/20238
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic258630b02e6ae86b1ee7ce663d9d026bf1c04e9
Gerrit-Change-Number: 20238
Gerrit-PatchSet: 1
Gerrit-Owner: Alexander Couzens <lynxis at fe80.eu>
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