[coreboot-gerrit] Change in coreboot[master]: mainboard/purism/librem13v2: Use common gpio macros
Hannah Williams (Code Review)
gerrit at coreboot.org
Fri Jun 16 03:07:43 CEST 2017
Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/20233
Change subject: mainboard/purism/librem13v2: Use common gpio macros
......................................................................
mainboard/purism/librem13v2: Use common gpio macros
Change-Id: Ib59feff18c8031f48c779d075285f5fa292e6f85
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/mainboard/purism/librem13v2/gpio.h
1 file changed, 26 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/20233/1
diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h
index 72f3da0..144f02e 100644
--- a/src/mainboard/purism/librem13v2/gpio.h
+++ b/src/mainboard/purism/librem13v2/gpio.h
@@ -21,72 +21,6 @@
#ifndef __ACPI__
-/* Redefine PAD_CFG_NF_1V8 using DRIVE0 RXEVCFG value */
-#undef PAD_CFG_NF_1V8
-#define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \
- _PAD_CFG_ATTRS(pad_, term_, \
- _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, \
- NO, NO, NO, NO, func_, YES, YES), PAD_FIELD(PAD_TOL, 1V8))
-
-/* Redefine PAD_CFG_GPI using DRIVE0 RXEVCFG value */
-#undef PAD_CFG_GPI
-#define PAD_CFG_GPI(pad_, term_, rst_) \
- _PAD_CFG_ATTRS(pad_, term_, \
- _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \
- GPIO, NO, YES), PAD_FIELD(HOSTSW, GPIO))
-
-/* Redefine PAD_CFG_GPO using DRIVE0 RXEVCFG value */
-#undef PAD_CFG_TERM_GPO
-#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
- _PAD_CFG(pad_, term_, \
- _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \
- GPIO, YES, NO) | PAD_FIELD_VAL(GPIOTXSTATE, val_))
-
-/* Create new macro PAD_CFG_NF_EVCFG to allow specifying the RXEVCFG value */
-#define PAD_CFG_NF_EVCFG(pad_, term_, rst_, func_, evcfg_) \
- _PAD_CFG(pad_, term_, \
- _DW0_VALS(rst_, RAW, NO, evcfg_, NO, NO, NO, NO, NO, NO, \
- func_, YES, YES))
-
-/* Redefine PAD_CFG_NF using DRIVE0 RXEVCFG value */
-#undef PAD_CFG_NF
-#define PAD_CFG_NF(pad_, term_, rst_, func_) \
- PAD_CFG_NF_EVCFG(pad_, term_, rst_, func_, DRIVE0)
-
-/* Define new PAD_CFG_NC_EVCFG macro which sets NC pad with custom RXEVCFG */
-#define PAD_CFG_NC_EVCFG(pad_, evcfg_, val_) \
- _PAD_CFG(pad_, NONE, \
- _DW0_VALS(DEEP, RAW, NO, evcfg_, NO, NO, NO, NO, NO, NO, \
- GPIO, YES, YES) | PAD_FIELD_VAL(GPIOTXSTATE, val_))
-
-/* Define new PAD_CFG_NC_RXINV macro which enables the RXINV value */
-#define PAD_CFG_NC_RXINV(pad_, evcfg_) \
- _PAD_CFG(pad_, NONE, \
- _DW0_VALS(DEEP, RAW, NO, evcfg_, NO, YES, NO, NO, NO, NO, \
- GPIO, YES, YES))
-
-/* Redefine PAD_CFG_NC using DRIVE0 RXEVCFG value */
-#undef PAD_CFG_NC
-#define PAD_CFG_NC(pad_) \
- PAD_CFG_NC_EVCFG(pad_, DRIVE0, 0)
-
-/* Define new PAD_CFG_NC_1 macro which sets GPIOTXSTATE to 1*/
-#define PAD_CFG_NC_1(pad_) \
- PAD_CFG_NC_EVCFG(pad_, DRIVE0, 1)
-
-/* Define new NC pad with 1v8 pad voltage tolerance */
-#define PAD_CFG_NC_1V8(pad_) \
- _PAD_CFG_ATTRS(pad_, NONE, \
- _DW0_VALS(DEEP, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \
- GPIO, YES, YES), PAD_FIELD(PAD_TOL, 1V8))
-
-/* Define new PAD_CFG_GPIO_APIC macro which enables both RX and TX */
-#define PAD_CFG_GPIO_APIC(pad_, val_, term_, rst_) \
- _PAD_CFG(pad_, term_, \
- _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, \
- GPIO, NO, NO) | PAD_FIELD_VAL(GPIOTXSTATE, val_))
-
-
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
@@ -96,12 +30,12 @@
/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PIRQA# */ PAD_CFG_NC_1(GPP_A7),
+/* PIRQA# */ PAD_CFG_NC(GPP_A7),
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
-/* PME# */ PAD_CFG_NC_EVCFG(GPP_A11, LEVEL, 0),
-/* BM_BUSY# */ PAD_CFG_NC_1(GPP_A12),
+/* PME# */ PAD_CFG_NC(GPP_A11),
+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* SUSACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
@@ -111,15 +45,15 @@
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
-/* ISH_GP4 */ PAD_CFG_NC_1(GPP_A22),
-/* ISH_GP5 */ PAD_CFG_NC_EVCFG(GPP_A23, LEVEL, 0),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
/* VRALERT# */ PAD_CFG_NC(GPP_B2),
-/* CPU_GP2 */ PAD_CFG_NC_EVCFG(GPP_B3, LEVEL, 0),
-/* CPU_GP3 */ PAD_CFG_NC_1(GPP_B4),
-/* SRCCLKREQ0# */ PAD_CFG_NF_EVCFG(GPP_B5, NONE, DEEP, NF1, LEVEL),
+/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
@@ -130,8 +64,8 @@
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
-/* GSPI0_CLK */ PAD_CFG_NC_RXINV(GPP_B16, LEVEL),
-/* GSPI0_MISO */ PAD_CFG_NC_RXINV(GPP_B17, EDGE),
+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU,
PLTRST, YES),
/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
@@ -174,10 +108,10 @@
/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
-/* ISH_SPI_CS# */ PAD_CFG_NC_EVCFG(GPP_D9, LEVEL, 0),
-/* ISH_SPI_CLK */ PAD_CFG_NC_EVCFG(GPP_D10, LEVEL, 0),
-/* ISH_SPI_MISO */ PAD_CFG_NC_EVCFG(GPP_D11, LEVEL, 0),
-/* ISH_SPI_MOSI */ PAD_CFG_NC_EVCFG(GPP_D12, LEVEL, 0),
+/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9),
+/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10),
+/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),
+/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
@@ -190,10 +124,10 @@
/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),
/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),
-/* SATAXPCI0 */ PAD_CFG_NC_EVCFG(GPP_E0, EDGE, 0),
+/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0),
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, NF1),
-/* CPU_GP0 */ PAD_CFG_NC_1(GPP_E3),
+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
@@ -205,28 +139,28 @@
/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-/* DDPD_HPD2 */ PAD_CFG_NC_RXINV(GPP_E15, EDGE),
+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),
/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NO),
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
-/* DDPD_CTRLCLK */ PAD_CFG_GPIO_APIC(GPP_E22, 0, NONE, DEEP),
+/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
-/* I2C2_SDA */ PAD_CFG_NC_1V8(GPP_F4),
-/* I2C2_SCL */ PAD_CFG_NC_1V8(GPP_F5),
-/* I2C3_SDA */ PAD_CFG_NC_1V8(GPP_F6),
-/* I2C3_SCL */ PAD_CFG_NC_1V8(GPP_F7),
+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
-/* I2C5_SDA */ PAD_CFG_NC_1V8(GPP_F10),
-/* I2C5_SCL */ PAD_CFG_NC_1V8(GPP_F11),
+/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),
+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),
/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
@@ -238,7 +172,7 @@
/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
-/* RSVD */ PAD_CFG_NC_EVCFG(GPP_F23, LEVEL, 0),
+/* RSVD */ PAD_CFG_NC(GPP_F23),
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
@@ -251,7 +185,7 @@
/* BATLOW# */ PAD_CFG_NC(GPD0),
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DSW_PWROK, NF1),
-/* LAN_WAKE# */ PAD_CFG_NC_EVCFG(GPD2, LEVEL, 0),
+/* LAN_WAKE# */ PAD_CFG_NC(GPD2),
/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DSW_PWROK, NF1),
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DSW_PWROK, NF1),
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DSW_PWROK, NF1),
--
To view, visit https://review.coreboot.org/20233
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib59feff18c8031f48c779d075285f5fa292e6f85
Gerrit-Change-Number: 20233
Gerrit-PatchSet: 1
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
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