[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Remove print wrongly showing ME PG-state

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20172


Change subject: soc/intel/skylake: Remove print wrongly showing ME PG-state
......................................................................

soc/intel/skylake: Remove print wrongly showing ME PG-state

As per discussion with CSME team, ME is NOT using PCI Config
Space register HFSTS2 Bit 10 to update ME power-gated status.

ME goes to CM0-PG state after ME device becomes idle after
Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C)
is being set.
And to retrieve the PG status of ME, one should read from the
PWRMBASE+offset 0x590 (which should give the value 0xF9) and
PWRMBASE+offset 0x594 (which should give the value 0xFF).

But, also it needs some time for the ME FW to go to idle state
and reflect these values in PWRMBASE registers after D0i3 bit
is being set. This does not happen instantly.

So, in CB, if we read the ME PG state in finalize.c, which happens
just after FSP Notify phase, where actually ME D0i3 bit is set,
we do not read the correct PG state values (i.e, 0xF9 and 0xFF).

But, once it boots to Kernel, if we read those same registers
through iotool mmio_read32 command, we get correct values.

SO, removing the ME PG state prints from Coreboot, since it is
actually showing wrong information, although ME Power Gating is
happening successfully.

Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/skylake/me.c
1 file changed, 0 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/20172/1

diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index 1865c00..afff053 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -250,8 +250,6 @@
 	       hfs.fields.d0i3_support_valid ? "YES" : "NO");
 	printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n",
 	       hfs2.fields.low_power_state ? "YES" : "NO");
-	printk(BIOS_DEBUG, "ME: Power Gated             : %s\n",
-	       hfs2.fields.power_gating_ind ? "YES" : "NO");
 	printk(BIOS_DEBUG, "ME: CPU Replaced            : %s\n",
 	       hfs2.fields.cpu_replaced_sts  ? "YES" : "NO");
 	printk(BIOS_DEBUG, "ME: CPU Replacement Valid   : %s\n",

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Gerrit-Change-Number: 20172
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>