[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Remove PCIe-PCI bridge

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20198


Change subject: soc/amd/stoneyridge: Remove PCIe-PCI bridge
......................................................................

soc/amd/stoneyridge: Remove PCIe-PCI bridge

The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs.  Remove this support from the source.

BUG=chrome-os-partner:62580062

Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/early_setup.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
D src/soc/amd/stoneyridge/pci.c
4 files changed, 0 insertions(+), 107 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20198/1

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index fe09c26..a836429 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -58,7 +58,6 @@
 ramstage-y += lpc.c
 ramstage-y += model_15_init.c
 ramstage-y += northbridge.c
-ramstage-y += pci.c
 ramstage-y += pcie.c
 ramstage-y += reset.c
 ramstage-y += sata.c
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index d3c9dd2..40723fa 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -58,39 +58,6 @@
 	u8 byte;
 	pci_devfn_t dev;
 
-	/* P2P Bridge */
-	dev = PCI_DEV(0, SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC);
-
-	/* Chip Control: Enable subtractive decoding */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
-
-	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
-	byte = pci_read_config8(dev, 0x4b);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4b, byte);
-
-	/* The same IO Base and IO Limit here is meaningful because we set the
-	 * bridge to be subtractive. During early setup stage, we have to make
-	 * sure that data can go through port 0x80.
-	 */
-	/* IO Base: 0xf000 */
-	byte = pci_read_config8(dev, 0x1c);
-	byte |= 0xf << 4;
-	pci_write_config8(dev, 0x1c, byte);
-
-	/* IO Limit: 0xf000 */
-	byte = pci_read_config8(dev, 0x1d);
-	byte |= 0xf << 4;
-	pci_write_config8(dev, 0x1d, byte);
-
-	/* PCI Command: Enable IO response */
-	byte = pci_read_config8(dev, 0x04);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x04, byte);
-
-	/* LPC controller */
 	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
 
 	byte = pci_read_config8(dev, 0x4a);
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index f044542..33973e2 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -90,12 +90,6 @@
 #define LPC_DEVID		0x780e
 #define LPC_DEVFN		PCI_DEVFN(LPC_DEV, LPC_FUNC)
 
-/* PCI Ports */
-#define SB_PCI_PORT_DEV		0x14
-#define SB_PCI_PORT_FUNC	4
-#define SB_PCI_PORT_DEVID	0x780f
-#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
-
 /* SD Controller */
 #define SD_DEV			0x14
 #define SD_FUNC			7
diff --git a/src/soc/amd/stoneyridge/pci.c b/src/soc/amd/stoneyridge/pci.c
deleted file mode 100644
index 61d7a39..0000000
--- a/src/soc/amd/stoneyridge/pci.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <soc/hudson.h>
-#include <amd_pci_util.h>
-#include <bootstate.h>
-
-static void pci_init(struct device *dev)
-{
-}
-
-/*
- * Update the PCI devices with a valid IRQ number
- * that is set in the mainboard PCI_IRQ structures.
- */
-static void set_pci_irqs(void *unused)
-{
-	/* Write PCI_INTR regs 0xC00/0xC01 */
-	write_pci_int_table();
-
-	/* Write IRQs for all devicetree enabled devices */
-	write_pci_cfg_irqs();
-}
-
-/*
- * Hook this function into the PCI state machine
- * on entry into BS_DEV_ENABLE.
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pci_init,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCI,
-};

-- 
To view, visit https://review.coreboot.org/20198
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Gerrit-Change-Number: 20198
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>