[coreboot-gerrit] Change in coreboot[master]: [WIP]nb/intel/x4x: Add some macros to clarify raminit code

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20196


Change subject: [WIP]nb/intel/x4x: Add some macros to clarify raminit code
......................................................................

[WIP]nb/intel/x4x: Add some macros to clarify raminit code

Change-Id: Ic64eff79cd10dd04d97ec998299b1415c2cf94e9
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/x4x.h
1 file changed, 68 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/20196/1

diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 7d8f5cc..c095d11 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -99,6 +99,74 @@
 
 #define SSKPD_MCHBAR		0x0c20 /* 64 bit */
 
+/* DLL settings for channel 0 */
+/*
+ * pi and tap settings for DQ DLL, used in write training
+ * bit 4-6: PI
+ * bit 0-3: TAP
+ */
+#define CH0_DQ_PITAP(lane, rank)	(0x500 + rank + 4 * lane)
+/*
+ * pi and tap settings for DQS DLL, used in write leveling
+ * bit 4-6: PI
+ * bit 0-3: TAP
+ */
+#define CH0_DQS_PITAP(lane, rank)	(0x520 + rank + 4 * lane)
+/*
+ * pi and tap settings for receiver DQS DLL, used in read training
+ * bit 4-6: PI
+ * bit 0-3: TAP
+ */
+#define CH0_RT_DQS_PITAP(lane)		(0x540 + lane * 4)
+/*
+ * pi and tap settings receiver enable DLL
+ * bit 4-6: PI
+ * bit 0-3: TAP
+ */
+#define CH0_RCVEN_PITAP(lane)		(0x560 + lane * 4)
+/*
+ * possible clkdelay are 0, 1, 2
+ * bit 31-16: DQS clkdelay, 2 bits per lane
+ * bit 15-0: DQ clkdelay, 2 bits per lane
+ */
+#define CH0_CLKDLY_DQDQS(rank)		(0x5c8 + 4 * rank)
+/*
+ * bit 16-9: DQ DBEn, one bit per lane
+ * bit 7-0: DQ DBSel, one bit per lane
+ */
+#define CH0_DQ_DBENSEL(rank)		(0x5a4 + 4 * rank)
+/*
+ * bit 16-9: DQS DBEn, one bit per lane
+ * bit 7-0: DQS DBSel, one bit per lane
+ */
+#define CH0_DQ_DBENSEL(rank)		(0x5a4 + 4 * rank)
+/*
+ * bits 0, 4, 8, 12, 16, 20, 24, 28: DQ coarse
+ * bits 1, 5, 9, 13, 17, 21, 25, 29: DQ coarse
+ */
+#define CH0_COARSE_DQDQS		0x5fc
+/*
+ * 2 bits per lane.
+ * This value (slave DLL) + the common min coarse (master DLL)
+ * represent the result from rcven calibration.
+ */
+#define CH0_COARSE_RCVEN_SLAVE		0x5fa
+/*
+ * bits 19:16 : common RCVEN coarse (master)
+ * bits 12:8 : tRD
+ */
+#define CH0_READ_SETTINGS		0x248
+/*
+ * 2 bits per bytelane: medium RCVEN control_reg_setup
+ * one carter clock per value.
+ */
+#define CH0_RCVEN_MEDIUM		0x58c
+/*
+ * bit 7: write leveling DQ high indicator
+ * bit 6: rcven DQS high indicator
+ */
+#define CH0_PROBE(lane)			(0x561 + lane * 4)
+
 /*
  * DMIBAR
  */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic64eff79cd10dd04d97ec998299b1415c2cf94e9
Gerrit-Change-Number: 20196
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>