[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: [WIP]Add common MP Init code
Barnali Sarkar (Code Review)
gerrit at coreboot.org
Tue Jun 13 17:19:07 CEST 2017
Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20189
Change subject: soc/intel/common/block: [WIP]Add common MP Init code
......................................................................
soc/intel/common/block: [WIP]Add common MP Init code
This patch contains State Machine callbacks init_cpus()
and post_cpu_init().
Also, it has the SOC call for CPU feature programming.
Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/common/block/cpu/Makefile.inc
A src/soc/intel/common/block/cpu/mp_init.c
A src/soc/intel/common/block/include/intelblocks/mp_init.h
3 files changed, 160 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/20189/1
diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc
index 42538445..5db7578 100644
--- a/src/soc/intel/common/block/cpu/Makefile.inc
+++ b/src/soc/intel/common/block/cpu/Makefile.inc
@@ -7,3 +7,4 @@
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += mp_init.c
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
new file mode 100644
index 0000000..c41c7d3
--- /dev/null
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Do essential initialization tasks before APs can be fired up -
+ *
+ * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
+ * that are set prior to ramstage.
+ * Real MTRRs programming are being done after resource allocation.
+ *
+ * Do, FSP loading before MP Init to ensure that the FSP cmponent stored in
+ * external stage cache in TSEG does not flush off due to SMM relocation
+ * during MP Init stage.
+ */
+
+/* MP initialization support. */
+
+#include <assert.h>
+#include <bootstate.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mp.h>
+#include <cpu/intel/microcode.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/msr.h>
+#include <soc/cpu.h>
+
+const void *microcode_patch;
+int ht_disabled;
+
+static struct device_operations cpu_dev_ops = {
+ .init = soc_core_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 },
+ { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },
+ { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 },
+ { X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 },
+ { X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 },
+ { X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 },
+ { X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0 },
+ { X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 },
+ { X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 },
+ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
+ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
+static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
+{
+ msr_t msr;
+ msr = rdmsr(MSR_CORE_THREAD_COUNT);
+ *num_virt = (msr.lo >> 0) & 0xffff;
+ *num_phys = (msr.lo >> 16) & 0xffff;
+}
+
+/* Find CPU topology */
+int get_cpu_count(void)
+{
+ unsigned int num_virt_cores, num_phys_cores;
+
+ read_cpu_topology(&num_phys_cores, &num_virt_cores);
+ ht_disabled = num_phys_cores == num_virt_cores;
+
+ printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
+ num_phys_cores, num_virt_cores);
+
+ return num_virt_cores;
+}
+
+void get_microcode_info(const void **microcode, int *parallel)
+{
+ microcode_patch = intel_microcode_find();
+ *microcode = microcode_patch;
+ *parallel = 1;
+ intel_microcode_load_unlocked(microcode_patch);
+}
+
+static void init_cpus(void *unused)
+{
+ device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
+ assert(dev != NULL);
+
+ soc_init_cpus(dev);
+}
+
+/* Ensure to re-program all MTRRs based on DRAM resource settings */
+static void post_cpus_init(void *unused)
+{
+ if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
+ printk(BIOS_ERR, "MTRR programming failure\n");
+
+ /* Temporarily cache the memory-mapped boot media. */
+ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
+ IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+ fast_spi_cache_bios_region();
+
+ x86_mtrr_check();
+}
+
+/* Do CPU MP Init before FSP Silicon Init */
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_cpus, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, post_cpus_init, NULL);
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
new file mode 100644
index 0000000..1e35c21
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_MP_INIT_H
+#define SOC_INTEL_COMMON_BLOCK_MP_INIT_H
+
+/* Supported CPUIDs */
+#define CPUID_SKYLAKE_C0 0x406e2
+#define CPUID_SKYLAKE_D0 0x406e3
+#define CPUID_SKYLAKE_HQ0 0x506e1
+#define CPUID_SKYLAKE_HR0 0x506e3
+#define CPUID_KABYLAKE_G0 0x406e8
+#define CPUID_KABYLAKE_H0 0x806e9
+#define CPUID_KABYLAKE_Y0 0x806ea
+#define CPUID_KABYLAKE_HA0 0x506e8
+#define CPUID_KABYLAKE_HB0 0x906e9
+#define CPUID_APOLLOLAKE_A0 0x506c8
+#define CPUID_APOLLOLAKE_B0 0x506c9
+
+int get_cpu_count(void);
+void get_microcode_info(const void **microcode, int *parallel);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Gerrit-Change-Number: 20189
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
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