[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: [WIP]Use CPU MP Init Common code
Barnali Sarkar (Code Review)
gerrit at coreboot.org
Tue Jun 13 17:19:08 CEST 2017
Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20190
Change subject: soc/intel/skylake: [WIP]Use CPU MP Init Common code
......................................................................
soc/intel/skylake: [WIP]Use CPU MP Init Common code
This patch uses the common CPU Mp Init file.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/cpu.h
3 files changed, 8 insertions(+), 95 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/20190/1
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 314afbf..e7fbb8a 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/mp_init.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/pch.h>
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 10b42dc..6293542 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -36,6 +36,7 @@
#include <delay.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/mp_init.h>
#include <pc80/mc146818rtc.h>
#include <soc/cpu.h>
#include <soc/msr.h>
@@ -45,9 +46,8 @@
#include <soc/smm.h>
#include <soc/systemagent.h>
-/* MP initialization support. */
-static const void *microcode_patch;
-static int ht_disabled;
+extern const void *microcode_patch;
+extern int ht_disabled;
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
@@ -394,7 +394,7 @@
}
/* All CPUs including BSP will run the following function. */
-static void cpu_core_init(device_t cpu)
+void soc_core_init(device_t cpu)
{
/* Clear out pending MCEs */
configure_mca();
@@ -428,70 +428,12 @@
configure_sgx(microcode_patch);
}
-static struct device_operations cpu_dev_ops = {
- .init = cpu_core_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 },
- { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },
- { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 },
- { X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 },
- { X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 },
- { X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 },
- { X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0 },
- { X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 },
- { X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 },
- { 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
-
-static int get_cpu_count(void)
-{
- msr_t msr;
- int num_threads;
- int num_cores;
-
- msr = rdmsr(MSR_CORE_THREAD_COUNT);
- num_threads = (msr.lo >> 0) & 0xffff;
- num_cores = (msr.lo >> 16) & 0xffff;
- printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
- num_cores, num_threads);
-
- ht_disabled = num_threads == num_cores;
-
- return num_threads;
-}
-
-static void get_microcode_info(const void **microcode, int *parallel)
-{
- microcode_patch = intel_microcode_find();
- *microcode = microcode_patch;
- *parallel = 1;
- intel_microcode_load_unlocked(microcode_patch);
-}
-
static int adjust_apic_id(int index, int apic_id)
{
if (ht_disabled)
return 2 * index;
else
return index;
-}
-
-/* Check whether the current CPU is the sibling hyperthread. */
-int is_secondary_thread(void)
-{
- int apic_id;
- apic_id = lapicid();
-
- if (!ht_disabled && (apic_id & 1))
- return 1;
- return 0;
}
static void per_cpu_smm_trigger(void)
@@ -537,10 +479,8 @@
.post_mp_init = post_mp_init,
};
-static void soc_init_cpus(void *unused)
+void soc_init_cpus(device_t dev)
{
- device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
- assert(dev != NULL);
struct bus *cpu_bus = dev->link_list;
if (mp_init_with_smm(cpu_bus, &mp_ops))
@@ -556,20 +496,6 @@
* and we shall not have this redundant call.
*/
configure_sgx(microcode_patch);
-}
-
-/* Ensure to re-program all MTRRs based on DRAM resource settings */
-static void soc_post_cpus_init(void *unused)
-{
- if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
- printk(BIOS_ERR, "MTRR programming failure\n");
-
- /* Temporarily cache the memory-mapped boot media. */
- if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
- IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
- fast_spi_cache_bios_region();
-
- x86_mtrr_check();
}
int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
@@ -594,7 +520,3 @@
return (msr1.lo & PRMRR_SUPPORTED) &&
(current_patch_id == new_patch_id - 1);
}
-
-/* Do CPU MP Init before FSP Silicon Init */
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL);
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 6419bf8..413d66a 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -23,17 +23,6 @@
/* CPU types */
#define SKYLAKE_FAMILY_ULT 0x406e0
-/* Supported CPUIDs */
-#define CPUID_SKYLAKE_C0 0x406e2
-#define CPUID_SKYLAKE_D0 0x406e3
-#define CPUID_SKYLAKE_HQ0 0x506e1
-#define CPUID_SKYLAKE_HR0 0x506e3
-#define CPUID_KABYLAKE_G0 0x406e8
-#define CPUID_KABYLAKE_H0 0x806e9
-#define CPUID_KABYLAKE_Y0 0x806ea
-#define CPUID_KABYLAKE_HA0 0x506e8
-#define CPUID_KABYLAKE_HB0 0x906e9
-
/* Latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76
@@ -67,7 +56,8 @@
u32 cpu_family_model(void);
u32 cpu_stepping(void);
int cpu_is_ult(void);
-int is_secondary_thread(void);
void configure_sgx(const void *microcode_patch);
+void soc_core_init(device_t cpu);
+void soc_init_cpus(device_t dev);
#endif
--
To view, visit https://review.coreboot.org/20190
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5
Gerrit-Change-Number: 20190
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
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