[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: [WIP]Use CPU MP Init Common code

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20191


Change subject: soc/intel/apollolake: [WIP]Use CPU MP Init Common code
......................................................................

soc/intel/apollolake: [WIP]Use CPU MP Init Common code

This patch uses the common CPU Mp Init file.

BUG=none
BRANCH=none
TEST=Build and boot reef

Change-Id: Ic28c4ac81e61e37670acee1e2233c27ce77de803
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/include/soc/cpu.h
2 files changed, 7 insertions(+), 72 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/20191/1

diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index ec202e4..9830cc7 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -30,6 +30,7 @@
 #include <fsp/api.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
 #include <reg_script.h>
 #include <romstage_handoff.h>
@@ -60,7 +61,7 @@
 	REG_SCRIPT_END
 };
 
-static void soc_core_init(device_t cpu)
+void soc_core_init(device_t cpu)
 {
 	/* Set core MSRs */
 	reg_script_run(core_msr_script);
@@ -72,21 +73,6 @@
 	enable_pm_timer_emulation();
 }
 
-static struct device_operations cpu_dev_ops = {
-	.init = soc_core_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
-	{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
-	{ 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
-
 /*
  * MP and SMM loading initialization.
  */
@@ -97,14 +83,6 @@
 };
 
 static struct smm_relocation_attrs relo_attrs;
-
-static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
-{
-	msr_t msr;
-	msr = rdmsr(MSR_CORE_THREAD_COUNT);
-	*num_virt = (msr.lo >> 0) & 0xffff;
-	*num_phys = (msr.lo >> 16) & 0xffff;
-}
 
 /*
  * Do essential initialization tasks before APs can be fired up -
@@ -120,28 +98,6 @@
 static void pre_mp_init(void)
 {
 	fsps_load(romstage_handoff_is_resume());
-}
-
-/* Find CPU topology */
-static int get_cpu_count(void)
-{
-	unsigned int num_virt_cores, num_phys_cores;
-
-	read_cpu_topology(&num_phys_cores, &num_virt_cores);
-
-	printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
-	       num_phys_cores, num_virt_cores);
-
-	return num_virt_cores;
-}
-
-static void get_microcode_info(const void **microcode, int *parallel)
-{
-	*microcode = intel_microcode_find();
-	*parallel = 1;
-
-	/* Make sure BSP is using the microcode from cbfs */
-	intel_microcode_load_unlocked(*microcode);
 }
 
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
@@ -201,32 +157,9 @@
 	.post_mp_init = southbridge_smm_enable_smi,
 };
 
-static void soc_init_cpus(void *unused)
+void soc_init_cpus(device_t dev)
 {
-	device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
-	assert(dev != NULL);
-
 	/* Clear for take-off */
 	if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
 		printk(BIOS_ERR, "MP initialization failure.\n");
 }
-
-/* Ensure to re-program all MTRRs based on DRAM resource settings */
-static void soc_post_cpus_init(void *unused)
-{
-	if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
-		printk(BIOS_ERR, "MTRR programming failure\n");
-
-	/* Temporarily cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
-		IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
-		fast_spi_cache_bios_region();
-
-	x86_mtrr_check();
-}
-
-/*
- * Do CPU MP Init before FSP Silicon Init
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL);
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 0e73d11..0bedf06 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -18,10 +18,12 @@
 #ifndef _SOC_APOLLOLAKE_CPU_H_
 #define _SOC_APOLLOLAKE_CPU_H_
 
-#define CPUID_APOLLOLAKE_A0	0x506c8
-#define CPUID_APOLLOLAKE_B0	0x506c9
+#include <arch/io.h>
 
 /* Common Timer Copy (CTC) frequency - 19.2MHz. */
 #define CTC_FREQ		19200000
 
+void soc_core_init(device_t cpu);
+void soc_init_cpus(device_t dev);
+
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic28c4ac81e61e37670acee1e2233c27ce77de803
Gerrit-Change-Number: 20191
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>