[coreboot-gerrit] Change in coreboot[master]: mainboard/google/{poppy, soraka}: Enable generation of SPI TP...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20142


Change subject: mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI node
......................................................................

mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI node

Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.

Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
3 files changed, 17 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/20142/1

diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index e133f9f..6a28fbf 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -7,6 +7,7 @@
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_MAX98927
+	select DRIVERS_SPI_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 7872a83..ad8dfc2 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -428,7 +428,14 @@
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				 register "hid" = "ACPI_DT_NAMESPACE_HID"
+				 register "compat_string" = ""google,cr50""
+				 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+				 device spi 0 on end
+			end
+		end # GSPI #0
 		device pci 1e.3 on  end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index c38bf93..e57cbd2 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -416,7 +416,14 @@
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				 register "hid" = "ACPI_DT_NAMESPACE_HID"
+				 register "compat_string" = ""google,cr50""
+				 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+				 device spi 0 on end
+			end
+		end # GSPI #0
 		device pci 1e.3 on  end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO

-- 
To view, visit https://review.coreboot.org/20142
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Gerrit-Change-Number: 20142
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>