[coreboot-gerrit] Change in coreboot[master]: google/fizz: Enable cr50 over i2c
Shelley Chen (Code Review)
gerrit at coreboot.org
Fri Jun 9 22:09:44 CEST 2017
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/20133
Change subject: google/fizz: Enable cr50 over i2c
......................................................................
google/fizz: Enable cr50 over i2c
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure verstage doesn't have any TPM errors
Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/fizz/gpio.h
3 files changed, 53 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/20133/1
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 2d2e6b7..2e2e134 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -13,11 +13,20 @@
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
select SOC_INTEL_KABYLAKE
+ select FIZZ_USE_I2C_TPM
select GENERIC_SPD_BIN
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+
+config DRIVER_TPM_I2C_BUS
+ depends on FIZZ_USE_I2C_TPM
+ default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+ depends on FIZZ_USE_I2C_TPM
+ default 0x50
config GBB_HWID
string
@@ -47,4 +56,17 @@
config DIMM_SPD_SIZE
int
default 512
+
+# Select this option to enable use of cr50 I2C TPM on fizz.
+config FIZZ_USE_I2C_TPM
+ bool
+ default y
+ select I2C_TPM
+ select MAINBOARD_HAS_I2C_TPM_CR50
+ select TPM2
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 64 # GPE0_DW2_00 (GPP_E0)
+
endif
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index ff2ec7f..abd5452 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -181,6 +181,12 @@
register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
+ # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
+ # for TPM communication before memory is up.
+ register "i2c[1]" = "{
+ .early_init = 1,
+ }"
+
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -214,7 +220,13 @@
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on
end # I2C #0
- device pci 15.1 on end # I2C #1
+ device pci 15.1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device i2c 50 on end
+ end
+ end # I2C #1
device pci 15.2 on end # I2C #2
device pci 15.3 off
end # I2C #3
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index ced33e9..6089469 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -108,8 +108,15 @@
/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP,
+ NF1), /* PCH_I2C1_H1_3V3_SDA */
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP,
+ NF1), /* PCH_I2C1_H1_3V3_SCL */
+#else
+/* I2C1_SDA */ PAD_CFG_NC(GPP_C18),
+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
+#endif
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */
@@ -231,10 +238,15 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
-/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,
- NF1), /* PCH_I2C2_H1_3V3_SDA */
-/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,
- NF1), /* PCH_I2C2_H1_3V3_SCL */
+#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)
+/* I2C2_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP,
+ NF1), /* PCH_I2C1_H1_3V3_SDA */
+/* I2C2_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP,
+ NF1), /* PCH_I2C1_H1_3V3_SCL */
+#else
+/* I2C2_SDA */ PAD_CFG_NF(GPP_C18),
+/* I2C2_SCL */ PAD_CFG_NF(GPP_C19),
+#endif
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
PLTRST), /* H1_PCH_INT_ODL */
/* Ensure UART pins are in native mode for H1. */
--
To view, visit https://review.coreboot.org/20133
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5
Gerrit-Change-Number: 20133
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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