[coreboot-gerrit] Change in coreboot[master]: google/fizz: Enable cr50 over SPI
Shelley Chen (Code Review)
gerrit at coreboot.org
Fri Jun 9 22:09:45 CEST 2017
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/20134
Change subject: google/fizz: Enable cr50 over SPI
......................................................................
google/fizz: Enable cr50 over SPI
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/fizz/gpio.h
3 files changed, 58 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/20134/1
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 2e2e134..9de2597 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -5,6 +5,7 @@
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
+ select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
@@ -27,6 +28,10 @@
config DRIVER_TPM_I2C_ADDR
depends on FIZZ_USE_I2C_TPM
default 0x50
+
+config DRIVER_TPM_SPI_BUS
+ depends on FIZZ_USE_SPI_TPM
+ default 0x1
config GBB_HWID
string
@@ -65,6 +70,14 @@
select MAINBOARD_HAS_I2C_TPM_CR50
select TPM2
+# Select this option to enable use of cr50 I2C TPM on fizz.
+config FIZZ_USE_SPI_TPM
+ bool
+ default n
+ select MAINBOARD_HAS_SPI_TPM_CR50
+ select SPI_TPM
+ select TPM2
+
config TPM_TIS_ACPI_INTERRUPT
int
default 64 # GPE0_DW2_00 (GPP_E0)
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index abd5452..f1d2b77 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -181,6 +181,13 @@
register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
+ # communication before memory is up.
+ register "gspi[0]" = "{
+ .speed_mhz = 1,
+ .early_init = 1,
+ }"
+
# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
# for TPM communication before memory is up.
register "i2c[1]" = "{
@@ -259,7 +266,14 @@
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
- device pci 1e.2 on end # GSPI #0
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.5 off end # SDIO
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index 6089469..f394fc3 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -80,10 +80,21 @@
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
-/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), /* PCH_SPI_H1_3V3_CS_L */
-/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), /* PCH_SPI_H1_3V3_CLK */
-/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), /* PCH_SPI_H1_3V3_MISO */
-/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), /* PCH_SPI_H1_3V3_MOSI */
+#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM)
+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CS_L */
+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CLK */
+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MISO */
+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MOSI */
+#else
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
+#endif
/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */
/* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */
/* GSPI1_MISO */ PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */
@@ -238,6 +249,21 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM)
+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CS_L */
+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CLK */
+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MISO */
+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MOSI */
+#else
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
+#endif
#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)
/* I2C2_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP,
NF1), /* PCH_I2C1_H1_3V3_SDA */
--
To view, visit https://review.coreboot.org/20134
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Gerrit-Change-Number: 20134
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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