[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: Add GPIO pad configuration
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Jun 9 17:02:17 CEST 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19934 )
Change subject: purism/librem13v2: Add GPIO pad configuration
......................................................................
purism/librem13v2: Add GPIO pad configuration
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).
Remove unnecessary early GPIO config.
Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
Reviewed-on: https://review.coreboot.org/19934
Reviewed-by: Matt DeVillier <matt.devillier at gmail.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/purism/librem13v2/Makefile.inc
D src/mainboard/purism/librem13v2/bootblock_mainboard.c
M src/mainboard/purism/librem13v2/devicetree.cb
M src/mainboard/purism/librem13v2/gpio.h
4 files changed, 211 insertions(+), 228 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc
index 4e2997e..6c8f38c 100644
--- a/src/mainboard/purism/librem13v2/Makefile.inc
+++ b/src/mainboard/purism/librem13v2/Makefile.inc
@@ -13,8 +13,6 @@
## GNU General Public License for more details.
##
-bootblock-y += bootblock_mainboard.c
-
romstage-y += pei_data.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/purism/librem13v2/bootblock_mainboard.c b/src/mainboard/purism/librem13v2/bootblock_mainboard.c
deleted file mode 100644
index 627b4e8..0000000
--- a/src/mainboard/purism/librem13v2/bootblock_mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-
-static void early_config_gpio(void)
-{
- /* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't do. We have to prepare certain gpios here
- * because of the brokenness in FSP. */
- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-void bootblock_mainboard_init(void)
-{
- early_config_gpio();
-}
diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index c8569d9b..0b49433 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -11,7 +11,7 @@
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h
index 614cfc0..72f3da0 100644
--- a/src/mainboard/purism/librem13v2/gpio.h
+++ b/src/mainboard/purism/librem13v2/gpio.h
@@ -19,232 +19,248 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
-/* EC in RW */
-#define GPIO_EC_IN_RW GPP_C6
-
-/* BIOS Flash Write Protect */
-#define GPIO_PCH_WP GPP_C23
-
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0 GPP_C12
-#define GPIO_MEM_CONFIG_1 GPP_C13
-#define GPIO_MEM_CONFIG_2 GPP_C14
-#define GPIO_MEM_CONFIG_3 GPP_C15
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE GPE0_LAN_WAK
-
-/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
-#define GPE_WLAN_WAKE GPE0_DW0_16
-
-/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
-#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
-
-/* Input device interrupt configuration */
-#define TOUCHPAD_INT_L GPP_B3_IRQ
-#define TOUCHSCREEN_INT_L GPP_E7_IRQ
-#define MIC_INT_L GPP_F10_IRQ
-
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
-#define EC_SCI_GPI GPE0_DW2_16
-#define EC_SMI_GPI GPP_E15
-
-/* Power rail control signals. */
-#define EN_PP3300_KEPLER GPP_C11
-#define EN_PP3300_DX_TOUCH GPP_C22
-#define EN_PP3300_DX_EMMC GPP_D5
-#define EN_PP1800_DX_EMMC GPP_D6
-#define EN_PP3300_DX_CAM GPP_D12
-
#ifndef __ACPI__
+
+/* Redefine PAD_CFG_NF_1V8 using DRIVE0 RXEVCFG value */
+#undef PAD_CFG_NF_1V8
+#define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \
+ _PAD_CFG_ATTRS(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, \
+ NO, NO, NO, NO, func_, YES, YES), PAD_FIELD(PAD_TOL, 1V8))
+
+/* Redefine PAD_CFG_GPI using DRIVE0 RXEVCFG value */
+#undef PAD_CFG_GPI
+#define PAD_CFG_GPI(pad_, term_, rst_) \
+ _PAD_CFG_ATTRS(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \
+ GPIO, NO, YES), PAD_FIELD(HOSTSW, GPIO))
+
+/* Redefine PAD_CFG_GPO using DRIVE0 RXEVCFG value */
+#undef PAD_CFG_TERM_GPO
+#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
+ _PAD_CFG(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \
+ GPIO, YES, NO) | PAD_FIELD_VAL(GPIOTXSTATE, val_))
+
+/* Create new macro PAD_CFG_NF_EVCFG to allow specifying the RXEVCFG value */
+#define PAD_CFG_NF_EVCFG(pad_, term_, rst_, func_, evcfg_) \
+ _PAD_CFG(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, evcfg_, NO, NO, NO, NO, NO, NO, \
+ func_, YES, YES))
+
+/* Redefine PAD_CFG_NF using DRIVE0 RXEVCFG value */
+#undef PAD_CFG_NF
+#define PAD_CFG_NF(pad_, term_, rst_, func_) \
+ PAD_CFG_NF_EVCFG(pad_, term_, rst_, func_, DRIVE0)
+
+/* Define new PAD_CFG_NC_EVCFG macro which sets NC pad with custom RXEVCFG */
+#define PAD_CFG_NC_EVCFG(pad_, evcfg_, val_) \
+ _PAD_CFG(pad_, NONE, \
+ _DW0_VALS(DEEP, RAW, NO, evcfg_, NO, NO, NO, NO, NO, NO, \
+ GPIO, YES, YES) | PAD_FIELD_VAL(GPIOTXSTATE, val_))
+
+/* Define new PAD_CFG_NC_RXINV macro which enables the RXINV value */
+#define PAD_CFG_NC_RXINV(pad_, evcfg_) \
+ _PAD_CFG(pad_, NONE, \
+ _DW0_VALS(DEEP, RAW, NO, evcfg_, NO, YES, NO, NO, NO, NO, \
+ GPIO, YES, YES))
+
+/* Redefine PAD_CFG_NC using DRIVE0 RXEVCFG value */
+#undef PAD_CFG_NC
+#define PAD_CFG_NC(pad_) \
+ PAD_CFG_NC_EVCFG(pad_, DRIVE0, 0)
+
+/* Define new PAD_CFG_NC_1 macro which sets GPIOTXSTATE to 1*/
+#define PAD_CFG_NC_1(pad_) \
+ PAD_CFG_NC_EVCFG(pad_, DRIVE0, 1)
+
+/* Define new NC pad with 1v8 pad voltage tolerance */
+#define PAD_CFG_NC_1V8(pad_) \
+ _PAD_CFG_ATTRS(pad_, NONE, \
+ _DW0_VALS(DEEP, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \
+ GPIO, YES, YES), PAD_FIELD(PAD_TOL, 1V8))
+
+/* Define new PAD_CFG_GPIO_APIC macro which enables both RX and TX */
+#define PAD_CFG_GPIO_APIC(pad_, val_, term_, rst_) \
+ _PAD_CFG(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, \
+ GPIO, NO, NO) | PAD_FIELD_VAL(GPIOTXSTATE, val_))
+
+
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
-/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
-/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
-/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
-/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PIRQA# */ PAD_CFG_NC(GPP_A7),
+/* PIRQA# */ PAD_CFG_NC_1(GPP_A7),
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
-/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
-/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP),
-/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
+/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+/* PME# */ PAD_CFG_NC_EVCFG(GPP_A11, LEVEL, 0),
+/* BM_BUSY# */ PAD_CFG_NC_1(GPP_A12),
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP),
-/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* SUSACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
-/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17),
+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
-/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
-/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
-/* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP),
-/* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP),
+/* ISH_GP4 */ PAD_CFG_NC_1(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC_EVCFG(GPP_A23, LEVEL, 0),
+
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
/* VRALERT# */ PAD_CFG_NC(GPP_B2),
-/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
-/* TRACKPAD_INT_L */
-/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */
-/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES),
-/* TRACKPAD WAKE */
-/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */
-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */
-/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
-/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
-/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
+/* CPU_GP2 */ PAD_CFG_NC_EVCFG(GPP_B3, LEVEL, 0),
+/* CPU_GP3 */ PAD_CFG_NC_1(GPP_B4),
+/* SRCCLKREQ0# */ PAD_CFG_NF_EVCFG(GPP_B5, NONE, DEEP, NF1, LEVEL),
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP),
+/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
-/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
-/* WLAN WAKE */
-/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
-/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP),
+/* GSPI0_CLK */ PAD_CFG_NC_RXINV(GPP_B16, LEVEL),
+/* GSPI0_MISO */ PAD_CFG_NC_RXINV(GPP_B17, EDGE),
+/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU,
+ PLTRST, YES),
/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
-/* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP),
-/* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */
-/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
-/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
-/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
-/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */
-/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */
-/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */
-/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */
-/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
-/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
-/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
-/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
-/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
-/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
-/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */
-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
-/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
-/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP),
-/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP),
-/* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP),
-/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP),
-/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
-/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
-/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
-/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
-/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
-/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9),
-/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */
-/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),
-/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
-/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
-/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
+/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
+
+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
+/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP),
+/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */
+/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* UART1_RXD */ PAD_CFG_NC(GPP_C12),
+/* UART1_TXD */ PAD_CFG_NC(GPP_C13),
+/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),
+/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),
+/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),
+/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),
+/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),
+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
+/* UART2_RXD */ PAD_CFG_NC(GPP_C20),
+/* UART2_TXD */ PAD_CFG_NC(GPP_C21),
+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),
+/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),
+
+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),
+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CS# */ PAD_CFG_NC_EVCFG(GPP_D9, LEVEL, 0),
+/* ISH_SPI_CLK */ PAD_CFG_NC_EVCFG(GPP_D10, LEVEL, 0),
+/* ISH_SPI_MISO */ PAD_CFG_NC_EVCFG(GPP_D11, LEVEL, 0),
+/* ISH_SPI_MOSI */ PAD_CFG_NC_EVCFG(GPP_D12, LEVEL, 0),
+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
-/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
-/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
-/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP),
-/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */
-/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */
+/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
+/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),
+/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),
+
+/* SATAXPCI0 */ PAD_CFG_NC_EVCFG(GPP_E0, EDGE, 0),
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
-/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
-/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */
+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, NF1),
+/* CPU_GP0 */ PAD_CFG_NC_1(GPP_E3),
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
-/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
-/* TOUCHSCREEN_INT_L */
+/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
/* SATALED# */ PAD_CFG_NC(GPP_E8),
-/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */
-/* USB2_OC1# */ PAD_CFG_NC(GPP_E10),
-/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */
-/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */
+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-/* USB_C0_DP_HPD */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-/* USB_C1_DP_HPD */
-/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
-/* EC_SMI_L */
-/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
-/* EC_SCI_L */
+/* DDPD_HPD2 */ PAD_CFG_NC_RXINV(GPP_E15, EDGE),
+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NO),
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP),
-/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */
-/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
-/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */
-/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
-/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
-/*
- * The next 4 pads are for bit banging the amplifiers. They are connected
- * together with i2s0 signals. For default behavior of i2s make these
- * gpio inupts.
- */
-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
-/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
-/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
-/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
-/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
-/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
-/* AUDIO1V8_SDA */
-/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
-/* AUDIO1V8_SCL */
-/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
-/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP),
-/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
-/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
-/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
-/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
-/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
-/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
-/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
-/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
-/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* RSVD */ PAD_CFG_NC(GPP_F23),
-/* SD_CMD */ PAD_CFG_NC(GPP_G0),
-/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
-/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
-/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
-/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
-/* SD_CD# */ PAD_CFG_NC(GPP_G5),
-/* SD_CLK */ PAD_CFG_NC(GPP_G6),
-/* SD_WP */ PAD_CFG_NC(GPP_G7),
-/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
-/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
-/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
-/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP),
-/* RSVD */ PAD_CFG_NC(GPD7),
-/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP),
-/* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP),
-/* LANPHYC */ PAD_CFG_NC(GPD11),
-};
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
+/* DDPD_CTRLCLK */ PAD_CFG_GPIO_APIC(GPP_E22, 0, NONE, DEEP),
+/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
-/* Early pad configuration in romstage. */
-static const struct pad_config early_gpio_table[] = {
-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
+/* I2C2_SDA */ PAD_CFG_NC_1V8(GPP_F4),
+/* I2C2_SCL */ PAD_CFG_NC_1V8(GPP_F5),
+/* I2C3_SDA */ PAD_CFG_NC_1V8(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC_1V8(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+/* I2C5_SDA */ PAD_CFG_NC_1V8(GPP_F10),
+/* I2C5_SCL */ PAD_CFG_NC_1V8(GPP_F11),
+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
+/* RSVD */ PAD_CFG_NC_EVCFG(GPP_F23, LEVEL, 0),
+
+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1),
+
+/* BATLOW# */ PAD_CFG_NC(GPD0),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DSW_PWROK, NF1),
+/* LAN_WAKE# */ PAD_CFG_NC_EVCFG(GPD2, LEVEL, 0),
+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DSW_PWROK, NF1),
+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DSW_PWROK, NF1),
+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DSW_PWROK, NF1),
+/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DSW_PWROK, NF1),
+/* RSVD */ PAD_CFG_NC_1(GPD7),
+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DSW_PWROK, NF1),
+/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DSW_PWROK, NF1),
+/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DSW_PWROK, NF1),
+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
};
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Gerrit-Change-Number: 19934
Gerrit-PatchSet: 4
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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