[coreboot-gerrit] Change in coreboot[master]: [WIP]cpu/intel/*: Add SMM SSE support
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Fri Jun 9 15:03:17 CEST 2017
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20127
Change subject: [WIP]cpu/intel/*: Add SMM SSE support
......................................................................
[WIP]cpu/intel/*: Add SMM SSE support
Add SMM fxsave/fxstore support.
Tested by hand and verified that modifing SSE registers in
SSM doesn't change register in protected mode.
Tested on GM45.
Change-Id: I0ca5be795ffd5f003f55213845ec221173cd4854
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/arch/x86/Kconfig
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_106cx/Kconfig
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/x86/smm/smmhandler.S
M src/include/cpu/x86/smm.h
M util/xcompile/xcompile
9 files changed, 154 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/20127/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e18d6d0..f3a81ee 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -64,6 +64,24 @@
Allow a platform or processor to select to be compiled using
the '-march=i586' option instead of the typical '-march=i686'
+config USE_MARCH_PENTIUM4
+ def_bool n
+ help
+ Allow a platform or processor to select to be compiled using
+ the '-march=pentium4' option instead of the typical '-march=i686'
+
+config USE_MARCH_SANDYBRIDGE
+ def_bool n
+ help
+ Allow a platform or processor to select to be compiled using
+ the '-march=sandybridge' option instead of the typical '-march=i686'
+
+config USE_MARCH_BROADWELL
+ def_bool n
+ help
+ Allow a platform or processor to select to be compiled using
+ the '-march=broadwell' option instead of the typical '-march=i686'
+
# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
# TODO: Improve description.
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index d6df9c0..5c91f48 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -27,6 +27,7 @@
select PARALLEL_CPU_INIT
select PARALLEL_MP
select CPU_INTEL_COMMON
+ select USE_MARCH_SANDYBRIDGE
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 2e154a3..c5a7de5 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -10,3 +10,4 @@
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
+ select USE_MARCH_PENTIUM4
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index f365cf1..1de84a9 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -13,6 +13,8 @@
select SUPPORT_CPU_UCODE_IN_CBFS
select SERIALIZED_SMM_INITIALIZATION
select CPU_INTEL_COMMON
+ select USE_MARCH_PENTIUM4
+
if CPU_INTEL_MODEL_106CX
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 59bb8d8..9a07d74 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -20,6 +20,7 @@
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
+ select USE_MARCH_PENTIUM4
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 6c04fba..d7fa230 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -21,6 +21,7 @@
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
select CPU_INTEL_COMMON
+ select USE_MARCH_SANDYBRIDGE
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index dd8a0c0..9eaae6b 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -117,6 +117,17 @@
orl $0x60000001, %eax /* CD, NW, PE = 1 */
movl %eax, %cr0
+ /* Enable SSE */
+ movl %cr4, %eax
+ orl $0x00040600, %eax /* set OSXSAVE, OSFXSR, OSXMMEXCPT */
+ movl %eax, %cr4
+
+ /* Configure xsave. XXX: Still needed ? */
+ xorl %ecx, %ecx
+ xorl %edx, %edx
+ movl $3, %eax
+ xsetbv
+
/* Enable protected mode */
data32 ljmp $0x08, $1f
@@ -179,9 +190,115 @@
movl (%ebx), %eax
pushl %eax
+ cmp $0x00030064, %eax
+ je smi_sse_save_00030064
+
+ cmp $0x00030100, %eax
+ je smi_sse_save_00030100
+
+ cmp $0x00030101, %eax
+ je smi_sse_save_00030101
+
+ /* fallthrough */
+smi_sse_save_legacy:
+ /* Compute address */
+ movl $(SMM_START + 0x8000 + 0x7e00 + 0x200), %eax
+ subl %ecx, %eax
+ movl %eax, %edx
+
+ /* Store address on stack */
+ popl %eax
+ pushl %edx
+ pushl %eax
+
+ /* Store FPU, MMX and SSE register */
+ fxsave (%edx)
+
/* Call 32bit C handler */
call smi_handler
+ /* Clean up */
+ addl $4, %esp
+
+ /* Get address from stack */
+ popl %ebx
+
+ /* Restore FPU, MMX and SSE register */
+ fxrstor (%ebx)
+
+ jmp smi_done
+
+smi_sse_save_00030100:
+ /* Compute address
+ * HACK !
+ * Range will overlap with next CPU,
+ * but content is marked reserved ...
+ * Assume it's save to use.
+ */
+ movl $(SMM_START + 0x8000 + 0x7d00 + 0x300), %eax
+ subl %ecx, %eax
+ movl %eax, %edx
+
+ /* Store address on stack */
+ popl %eax
+ pushl %edx
+ pushl %eax
+
+ /* Store FPU, MMX and SSE register */
+ fxsave (%edx)
+
+ /* Call 32bit C handler */
+ call smi_handler
+
+ /* Clean up */
+ addl $4, %esp
+
+ /* Get address from stack */
+ popl %ebx
+
+ /* Restore FPU, MMX and SSE register */
+ fxrstor (%ebx)
+
+ jmp smi_done
+
+smi_sse_save_00030101:
+ /* Compute address */
+ movl $(SMM_START + 0x8000 + 0x7c00), %eax
+ subl %ecx, %eax
+ movl %eax, %edx
+
+ /* Store address on stack */
+ popl %eax
+ pushl %edx
+ pushl %eax
+
+ /* Store FPU, MMX and SSE register */
+ fxsave (%edx)
+
+ /* Call 32bit C handler */
+ call smi_handler
+
+ /* Clean up */
+ addl $4, %esp
+
+ /* Get address from stack */
+ popl %edx
+
+ /* Restore FPU, MMX and SSE register */
+ fxrstor (%edx)
+
+ jmp smi_done
+
+smi_sse_save_00030064:
+ /* Call 32bit C handler */
+ call smi_handler
+
+ /* Clean up */
+ addl $4, %esp
+
+ jmp smi_done
+
+smi_done:
/* To return, just do rsm. It will "clean up" protected mode */
rsm
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 1892119..95ef8de 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -131,7 +131,7 @@
* starts @ 0x7d00
*/
typedef struct {
- u8 reserved0[208];
+ u8 reserved0[208]; /* FXSAVE */
u32 gdtr_upper_base;
u32 ldtr_upper_base;
@@ -202,6 +202,10 @@
u64 cr3;
u64 cr0;
+
+ u8 reserved5[64];
+ u8 reserved6[256]; /* FXSAVE */
+
} __attribute__((packed)) em64t_smm_state_save_area_t;
@@ -428,6 +432,7 @@
u32 eflags;
u32 cr3;
u32 cr0;
+ u8 reserved4[512]; /* FXSAVE */
} __attribute__((packed)) legacy_smm_state_save_area_t;
typedef enum {
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 347ae8e..d4c2905 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -236,7 +236,13 @@
cat <<EOF
ifeq (\$(CONFIG_USE_MARCH_586),y)
- GCC_CFLAGS_${TARCH} += -march=i586
+ GCC_CFLAGS_${TARCH} += -march=i586 -msse
+else ifeq (\$(CONFIG_USE_MARCH_PENTIUM4),y)
+ GCC_CFLAGS_${TARCH} += -march=pentium4
+else ifeq (\$(CONFIG_USE_MARCH_SANDYBRIDGE),y)
+ GCC_CFLAGS_${TARCH} += -march=sandybridge -mno-avx
+else ifeq (\$(CONFIG_USE_MARCH_BROADWELL),y)
+ GCC_CFLAGS_${TARCH} += -march=sandybridge -mno-avx -mno-avx2
else
GCC_CFLAGS_${TARCH} += -march=i686
endif
--
To view, visit https://review.coreboot.org/20127
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0ca5be795ffd5f003f55213845ec221173cd4854
Gerrit-Change-Number: 20127
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
More information about the coreboot-gerrit
mailing list