[coreboot-gerrit] Change in coreboot[master]: riscv: Update the gcc built-in macro __riscv__

[Anonymous Coward (Code Review)]

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20125


Change subject: riscv: Update the gcc built-in macro __riscv__
......................................................................

riscv: Update the gcc built-in macro __riscv__

The architecture is determined by __riscv__ in the LZ4_copy8 function
(located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1.
But __riscv__ does not exist.

Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792
Signed-off-by: wxjstz <wxjstz at 126.com>
---
M src/commonlib/lz4_wrapper.c
1 file changed, 2 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/20125/1

diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c
index e444f2c..c2014cc 100644
--- a/src/commonlib/lz4_wrapper.c
+++ b/src/commonlib/lz4_wrapper.c
@@ -48,6 +48,7 @@
 /* ARM32 needs to be a special snowflake to prevent GCC from coalescing the
  * access into LDRD/STRD (which don't support unaligned accesses). */
 #ifdef __arm__	/* ARMv < 6 doesn't support unaligned accesses at all. */
+
 	#if defined(__COREBOOT_ARM_ARCH__) && __COREBOOT_ARM_ARCH__ < 6
 		int i;
 		for (i = 0; i < 8; i++)
@@ -67,7 +68,7 @@
 			: "=m"(*(uint32_t *)(dst + 4))
 			: [x1]"r"(x1), [dst]"r"(dst));
 	#endif
-#elif defined(__riscv__)
+#elif defined(__riscv__) || defined(__riscv)
 	/* RISC-V implementations may trap on any unaligned access. */
 	int i;
 	for (i = 0; i < 8; i++)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792
Gerrit-Change-Number: 20125
Gerrit-PatchSet: 1
Gerrit-Owner: Anonymous Coward #1001664