[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add USB port number information to wake s...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/20122 )

Change subject: soc/intel/skylake: Add USB port number information to wake source
......................................................................

soc/intel/skylake: Add USB port number information to wake source

USB port status register can be used to decide if a particular port
was responsible for generating PME# resulting in device wake:
1. CSC bit is set and port is capable of waking on connect/disconnect
2. PLC bit is set and port is in resume state

BUG=b:37088992
TEST=Verified with wake on USB2.0 port 3, mosys shows:

19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3

Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/elog.c
1 file changed, 120 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/20122/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468
Gerrit-Change-Number: 20122
Gerrit-PatchSet: 2
Gerrit-Owner: Furquan Shaikh <furquan at google.com>