[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Add SMBIOS table 17 generation

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20119


Change subject: nb/intel/gm45: Add SMBIOS table 17 generation
......................................................................

nb/intel/gm45: Add SMBIOS table 17 generation

Some things like DIMM number and memory type are hardcoded due to
raminit not supporting multiple DIMMs per channel and ddr3.

TESTED on Thinkpad X200.

Change-Id: I16c005baee900b56a4b0c76bb880105c06c518a7
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/t400/romstage.c
M src/mainboard/lenovo/x200/romstage.c
M src/mainboard/roda/rk9/romstage.c
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/raminit.c
5 files changed, 59 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/20119/1

diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 31a80a4..561893d 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -168,6 +168,8 @@
 
 	cbmem_initted = !cbmem_recovery(s3resume);
 
+	fill_smbios17(&sysinfo);
+
 	romstage_handoff_init(cbmem_initted && s3resume);
 
 	printk(BIOS_SPEW, "exit main()\n");
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 49c5528..1a3edb9 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -159,6 +159,8 @@
 
 	cbmem_initted = !cbmem_recovery(s3resume);
 
+	fill_smbios17(&sysinfo);
+
 	romstage_handoff_init(cbmem_initted && s3resume);
 
 	printk(BIOS_SPEW, "exit main()\n");
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 720f628..28ac41b 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -189,6 +189,8 @@
 
 	cbmem_initted = !cbmem_recovery(s3resume);
 
+	fill_smbios17(&sysinfo);
+
 	romstage_handoff_init(cbmem_initted && s3resume);
 
 	printk(BIOS_SPEW, "exit main()\n");
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 34f734c..85ce363 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -415,6 +415,7 @@
 void enter_raminit_or_reset(void);
 void get_gmch_info(sysinfo_t *);
 void raminit(sysinfo_t *, int s3resume);
+void fill_smbios17(const sysinfo_t *ctrl);
 void raminit_thermal(const sysinfo_t *);
 void init_igd(const sysinfo_t *const);
 void init_pm(const sysinfo_t *, int do_freq_scaling_cfg);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 30e9297..d4f2111 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -18,10 +18,14 @@
 #include <stdlib.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <cbmem.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <device/device.h>
+#include <memory_info.h>
+#include <smbios.h>
 #include <spd.h>
+#include <string.h>
 #include <console/console.h>
 #include <lib.h>
 #include <delay.h>
@@ -1705,6 +1709,54 @@
 	MCHBAR32(0x15f0) |=  (1 << 10);
 }
 
+void fill_smbios17(const sysinfo_t *ctrl)
+{
+	struct memory_info *mem_info;
+	int channel;
+	struct dimm_info *dimm;
+	u16 ddr_freq = 0;
+
+	switch (ctrl->selected_timings.mem_clock) {
+	case MEM_CLOCK_533MHz:
+		ddr_freq = 533;
+		break;
+	case MEM_CLOCK_400MHz:
+		ddr_freq = 400;
+		break;
+	case MEM_CLOCK_333MHz:
+		ddr_freq = 333;
+		break;
+	}
+
+	/*
+	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
+	 * table 17
+	 */
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
+	if (mem_info == NULL)
+		return;
+
+	memset(mem_info, 0, sizeof(*mem_info));
+
+	/* Assumes one slot per channel */
+	FOR_EACH_POPULATED_CHANNEL(ctrl->dimms, channel) {
+		dimm = &(mem_info->dimm[mem_info->dimm_cnt]);
+		dimm->ddr_type = MEMORY_TYPE_DDR3;
+		dimm->ddr_frequency = ddr_freq;
+		dimm->dimm_size = ctrl->dimms[channel].rank_capacity_mb *
+			ctrl->dimms[channel].ranks;
+		dimm->channel_num = channel;
+		dimm->rank_per_dimm = ctrl->dimms[channel].ranks;
+		dimm->dimm_num = 0;
+		/* We skip module part number, manufacturer id since SPD */
+		/* reading is slow */
+		dimm->mod_type = ctrl->dimms[channel].card_type;
+		dimm->bus_width = 0x3; /* 64 bit ? */
+		mem_info->dimm_cnt++;
+	}
+}
+
 void raminit(sysinfo_t *const sysinfo, const int s3resume)
 {
 	const dimminfo_t *const dimms = sysinfo->dimms;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I16c005baee900b56a4b0c76bb880105c06c518a7
Gerrit-Change-Number: 20119
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>